Inventor
Ephrem G. Gebreselasie
Inventor
South Burlington, VT, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices29%
H01LSemiconductor devices14%
G06FElectric digital data processing12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
G01RMeasuring electric variables8%
G11BInformation storage based on relative movement between record carrier and transducer6%
H02HEmergency protective circuit arrangements6%
G11CStatic stores4%
G09GArrangements or circuits for control of indicating devices using static means to present variable information2%
H01GCapacitors2%
PatentTitleYear
10,985,156Electrostatic discharge clamp with reduced off-state power consumption202110,636,872Apparatus and method to prevent integrated circuit from entering latch-up mode202010,263,418Method to protect sensitive devices from electrostatic discharge damage201910,008,848Method to protect sensitive devices from electrostatic discharge damage20189,940,986Electrostatic discharge protection structures for eFuses20189,601,139'Electrostatic discharge protection for a magnetoresistive sensor'20179,568,538'Matching of bipolar transistor pair through electrical stress'20179,318,217'Programming an electrical fuse with a silicon-controlled rectifier'20169,279,862'Electrostatic discharge protection for a magnetoresistive sensor'20169,034,712'Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage'20158,946,799'Silicon controlled rectifier with stress-enhanced adjustable trigger voltage'20158,908,334'Electrostatic discharge protection for a magnetoresistive sensor'20148,598,660'Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage'20138,586,423'Silicon controlled rectifier with stress-enhanced adjustable trigger voltage'20138,530,319'Vertical silicide e-fuse'20138,159,040'Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor'20128,054,597'Electrostatic discharge structures and methods of manufacture'20118,044,510'Product and method for integration of deep trench mesh and structures under a bond pad'20117,876,547'Vertical parallel plate capacitor structures'20117,482,258'Product and method for integration of deep trench mesh and structures under a bond pad'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2018Patents assigned to IBM (15)· patent assignee history
2009–2011Based in Shelburne, VT, US· patent location history
2011–2021Based in South Burlington, VT, US· patent location history
2012–2013Patents assigned to GEBRESELASIE EPHREM G (4)· patent assignee history
2013Patents assigned to CAMILLO-CASTILLO RENATA (2)· patent assignee history
2013Patents assigned to GAUTHIER JR ROBERT J (2)· patent assignee history
2016–2020Patents assigned to GLOBALFOUNDRIES INC (5)· patent assignee history
2018Based in Burlington, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 15 | 2009–2018 |
| GLOBALFOUNDRIES INC | 5 | 2016–2020 |
| GEBRESELASIE EPHREM Gself | 4 | 2012–2013 |
| CAMILLO-CASTILLO RENATA | 2 | 2013 |
| GAUTHIER JR ROBERT J | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 16 | 2011–2021 |
| Shelburne, VT, US | 3 | 2009–2011 |
| Burlington, VT, US | 1 | 2018 |