Inventor
Ernest J. Russell
Inventor
Richmond, TX, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H05KPrinted circuits16%
Y02PClimate change mitigation technologies in the production or processing of goods12%
Y10TTechnical subjects covered by former us classification12%
D06PDyeing or printing textiles10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
H01GCapacitors2%
PatentTitleYear
6,784,367'Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies'20046,548,757'Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies'20036,465,278'Method and apparatus for delivering electrical power to a semiconductor die'20026,268,643'Lead frame device for delivering electrical power to a semiconductor die'20016,040,983'Vertical passive components for surface mount assembly'20005,671,125'Vertical package mounted on both sides of a printed circuit board'19975,637,828'High density semiconductor package'19975,600,178'Semiconductor package having interdigitated leads'19975,589,420'Method for a hybrid leadframe-over-chip semiconductor package'19965,545,920'Leadframe-over-chip having off-chip conducting leads for increased bond pad connectivity'19965,534,729'Integrated circuit lead frame for coupling to non-neighboring bond pads'19965,521,426'Reduced capacitance lead frame for lead on chip package'19965,483,024'High density semiconductor package'19965,432,678'High power dissipation vertical mounted package for surface mount application'19955,413,970'Process for manufacturing a semiconductor package having two rows of interdigitated leads'19955,396,701'Method for packaging an integrated circuit'19955,275,975'Method of making a relatively flat semiconductor package having a semiconductor chip encapsulated in molded material'19945,260,601'Edge-mounted, surface-mount package for semiconductor integrated circuit devices'19935,231,305'Ceramic bonding bridge'19934,975,763'Edge-mounted, surface-mount package for semiconductor integrated circuit devices'19904,878,920'Process for the continuous dyeing of industrial nylon'19894,832,699'Continuous process for dyeing nylon fabrics'19894,812,140'Continuous aqueous dyeing process for high-tenacity industrial nylon fabrics'19894,759,770'Process for simultaneously dyeing and improving the flame-resistant properties of aramid fibers'19884,749,378'Process for improving the flame-resistant properties of aramid fibers'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–1989Patents assigned to BURLINGTON INDUSTRIES INC (5)· patent assignee history
1988–1989Based in Greensboro, NC, US· patent location history
1990–2002Patents assigned to TEXAS INSTRUMENTS INC (18)· patent assignee history
1990–2002Based in Richmond, TX, US· patent location history
2003–2004Patents assigned to MICRON TECHNOLOGY INC (2)· patent assignee history
2003–2004Based in McKinney, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 18 | 1990–2002 |
| BURLINGTON INDUSTRIES INC | 5 | 1988–1989 |
| MICRON TECHNOLOGY INC | 2 | 2003–2004 |
Locations
| Location | Patents | Span |
|---|---|---|
| Richmond, Texas, US | 18 | 1990–2002 |
| Greensboro, NC, US | 5 | 1988–1989 |
| McKinney, Texas, US | 2 | 2003–2004 |