Inventor
Sudarsan Uppili
Inventor
Portland, OR, US
Overview
Patents· 10 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices50%
H01LSemiconductor devices31%
H03HImpedance networks, e.g. resonant circuits13%
Y10TTechnical subjects covered by former us classification6%
PatentTitleYear
9,673,316'Vertical semiconductor device having frontside interconnections'20179,450,074'LDMOS with field plate connected to gate'20169,209,091'Integrated monolithic galvanic isolator'20159,171,916'LDMOS with thick interlayer-dielectric layer'20159,070,714'Strapped dual-gate VDMOS device'20158,643,067'Strapped dual-gate VDMOS device'20147,966,722'Planarization method in the fabrication of a circuit'20117,768,364'Bulk acoustic resonators with multi-layer electrodes'20106,773,973'Semiconductor transistor having a polysilicon emitter and methods of making the same'20046,593,640'Bipolar transistor and methods of forming bipolar transistors'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2017Patents assigned to MAXIM INTEGRATED PRODUCTS (9)· patent assignee history
2003–2017Based in Portland, OR, US· patent location history
2014–2016Patents assigned to UPPILI SUDARSAN (4)· patent assignee history
2015–2016Patents assigned to BOUCHE GUILLAUME (3)· patent assignee history
2015Patents assigned to SNYDER DAVID L (2)· patent assignee history
2015–2016Patents assigned to YANG FANLING HSU (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MAXIM INTEGRATED PRODUCTS | 9 | 2003–2017 |
| UPPILI SUDARSANself | 4 | 2014–2016 |
| BOUCHE GUILLAUME | 3 | 2015–2016 |
| SNYDER DAVID L | 2 | 2015 |
| YANG FANLING HSU | 2 | 2015–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 10 | 2003–2017 |