Inventor
Peter D. MacWilliams
Inventor
Aloha, OR, US
Overview
Patents· 61 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing80%
G11CStatic stores14%
H04LTransmission of digital information, e.g. telegraphic communication3%
H01RElectrically-conductive connections1%
H05KPrinted circuits1%
PatentTitleYear
8,866,830'Memory controller interface for micro-tiled memory access'20148,310,854'Identifying and accessing individual memory devices in a memory channel'20128,253,751'Memory controller interface for micro-tiled memory access'20128,200,883'Micro-tile memory interfaces'20128,064,237'Identifying and accessing individual memory devices in a memory channel'20118,032,688'Micro-tile memory interfaces'20117,872,892'Identifying and accessing individual memory devices in a memory channel'2011RE040921'Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system'2009RE038388'Method and apparatus for performing deferred transactions'20046,633,947'Memory expansion channel for propagation of control and request packets'20036,598,103'Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system'20036,587,912'Method and apparatus for implementing multiple memory buses on a memory module'20036,519,735'Method and apparatus for detecting errors in data output from memory and a device failure in the memory'20036,477,614'Method for implementing multiple memory buses on a memory module'20026,442,632'System resource arbitration mechanism for a host bridge'20026,412,060'Method and apparatus for supporting multiple overlapping address spaces on a shared bus'20026,405,271'Data flow control mechanism for a bus supporting two-and three-agent transactions'20026,397,291'Method and apparatus for retrieving data from a data storage device'20026,336,159'Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system'20026,253,302'Method and apparatus for supporting multiple overlapping address spaces on a shared bus'20016,247,136'Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environment'20016,226,757'Apparatus and method for bus timing compensation'20016,212,589'System resource arbitration mechanism for a host bridge'20016,209,072'Source synchronous interface between master and slave using a deskew latch'20016,202,125'Processor-cache protocol using simple commands to implement a range of cache configurations'20016,192,459'Method and apparatus for retrieving data from a data storage device'20016,128,748'Independent timing compensation of write data path and read data path on a common data bus'20006,112,016'Method and apparatus for sharing a signal line between agents'20006,075,730'High performance cost optimized memory with delayed memory writes'20006,012,118'Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus'20005,996,042'Scalable, high bandwidth multicard memory system utilizing a single memory controller'19995,961,621'Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system'19995,948,094'Method and apparatus for executing multiple transactions within a single arbitration cycle'19995,937,171'Method and apparatus for performing deferred transactions'19995,923,857'Method and apparatus for ordering writeback data transfers on a bus'19995,919,254'Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system'19995,911,053'Method and apparatus for changing data transfer widths in a computer system'19995,906,001'Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines'19995,905,876'Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system'19995,903,916'Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation'19995,822,767'Method and apparartus for sharing a signal line between agents'19985,818,794'Internally controlled signal system for controlling the operation of a device'19985,796,977'Highly pipelined bus architecture'19985,784,579'Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth'19985,651,137'Scalable cache attributes for an input/output bus'19975,625,779'Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge'19975,615,343'Method and apparatus for performing deferred transactions'19975,572,703'Method and apparatus for snoop stretching using signals that convey snoop results'19965,555,423'Multi-mode microprocessor having a pin for resetting its register without purging its cache'19965,537,640'Asynchronous modular bus architecture with cache consistency'19965,513,331'Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset'19965,488,639'Parallel multistage synchronization method and apparatus'19965,471,637'Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer'19955,455,957'Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol'19955,421,734'Method and apparatus for evolving bus from five volt to three point three volt operation'19955,355,467'Second level cache controller unit and system'19945,301,299'Optimized write protocol for memory accesses utilizing row and column strobes'19945,293,603'Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path'19945,239,638'Two strobed memory access'19935,228,134'Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus'19934,785,396'Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–2014Patents assigned to INTEL CORP (61)· patent assignee history
1988–2014Based in Aloha, OR, US· patent location history
2011–2014Patents assigned to AKIYAMA JAMES (5)· patent assignee history
2011–2014Patents assigned to GABEL DOUGLAS (5)· patent assignee history
2011–2014Patents assigned to MACWILLIAMS PETER (5)· patent assignee history
2011–2012Patents assigned to BAINS KULJIT S (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 61 | 1988–2014 |
| AKIYAMA JAMES | 5 | 2011–2014 |
| GABEL DOUGLAS | 5 | 2011–2014 |
| MACWILLIAMS PETERself | 5 | 2011–2014 |
| BAINS KULJIT S | 2 | 2011–2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Aloha, OR, US | 61 | 1988–2014 |