Inventor

Michael Ignatowski

Inventor

Austin, TX, US

Overview

37→

Patents

1993–2021

Patent span

Physics

Primary field (CPC G)

Patents· 37 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing42%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use17%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

G11CStatic stores9%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%

H03KPulse technique4%

H04LTransmission of digital information, e.g. telegraphic communication4%

H10DInorganic electric semiconductor devices3%

G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%

H01LSemiconductor devices1%

PatentTitleYear

11,061,572Memory object tagged memory monitoring method and system2021 10,956,536Device and method for accelerating matrix multiply operations2021 10,902,087Device and method for accelerating matrix multiply operations as a sum of outer products2021 10,817,422Data processing system with decoupled data operations2020 10,579,557Near-memory hardened compute blocks for configurable computing substrates2020 10,482,043Nondeterministic memory access requests to non-volatile memory2019 10,318,153Techniques for changing management modes of multilevel memory hierarchy2019 9,804,996'Computation memory operations in a logic layer of a stacked memory'2017 9,755,964'Multi-protocol header generation system'2017 9,727,241'Memory page access detection'2017 9,697,147'Stacked memory device with metadata management'2017 9,535,627'Latency-aware memory control'2017 9,472,299'Methods and systems for mitigating memory drift'2016 9,377,954'System and method for memory allocation in a multiclass memory system'2016 9,344,091'Die-stacked memory device with reconfigurable logic'2016 9,235,528'Write endurance management techniques in the logic layer of a stacked memory'2016 9,201,777'Quality of service support using stacked memory device with logic die'2015 9,170,948'Cache coherency using die-stacked memory device with logic die'2015 9,135,185'Die-stacked memory device providing data translation'2015 8,922,243'Die-stacked memory device with reconfigurable logic'2014 8,879,301'Method and apparatus for controlling state information retention in an apparatus'2014 8,806,182'Multiple-core processor supporting multiple instruction set architectures'2014 8,686,559'Semiconductor chip stacking for redundancy and yield improvement'2014 8,597,960'Semiconductor chip stacking for redundancy and yield improvement'2013 8,122,216'Systems and methods for masking latency of memory reorganization work in a compressed memory system'2012 8,028,290'Multiple-core processor supporting multiple instruction set architectures'2011 7,668,096'Apparatus for modeling queueing systems with highly variable traffic arrival rates'2010 7,647,519'System and computer program product for dynamically managing power in microprocessor chips according to present processing demands'2010 7,484,043'Multiprocessor system with dynamic cache coherency regions'2009 7,401,240'Method for dynamically managing power in microprocessor chips according to present processing demands'2008 7,376,083'Apparatus and method for modeling queueing systems with highly variable traffic arrival rates'2008 7,099,816'Method, system and article of manufacture for an analytic modeling technique for handling multiple objectives'2006 6,768,968'Method and system of an integrated simulation tool using business patterns and scripts'2004 6,457,100'Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls'2002 5,895,487'Integrated processing and L2 DRAM cache'1999 5,875,470'Multi-port multiple-simultaneous-access DRAM chip'1999 5,265,232'Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2014Patents assigned to IBM (15)· patent assignee history

1993–2014Based in Red Hook, NY, US· patent location history

2012–2017Patents assigned to IGNATOWSKI MICHAEL (9)· patent assignee history

2014–2021Patents assigned to ADVANCED MICRO DEVICES INC (21)· patent assignee history

2014–2021Based in Austin, TX, US· patent location history

2015–2017Patents assigned to BECKMANN BRADFORD M (4)· patent assignee history

2015–2017Patents assigned to LOH GABRIEL H (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	21	2014–2021
IBM	15	1993–2014
IGNATOWSKI MICHAELself	9	2012–2017
BECKMANN BRADFORD M	4	2015–2017
LOH GABRIEL H	4	2015–2017

Locations

Location	Patents	Span
Austin, Texas, US	21	2014–2021
Red Hook, New York, US	16	1993–2014