Inventor
Alexei Sadovnikov
Inventor
Sunnyvale, CA, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices42%
H01LSemiconductor devices26%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
PatentTitleYear
11,094,806Fabricating transistors with implanting dopants at first and second dosages in the collector region to form the base region202111,081,558LDMOS with high-k drain STI dielectric202111,049,967DMOS transistor having thick gate oxide and STI and method of fabricating202111,024,649Integrated circuit with resurf region biasing under buried insulator layers202110,978,559MOS transistor with folded channel and folded drift region202110,886,160Sinker to buried layer connection region for narrow deep trenches202110,811,543Semiconductor device with deep trench isolation and trench capacitor202010,636,815Integrated circuit with resurf region biasing under buried insulator layers202010,593,773LDMOS with high-k drain STI dielectric202010,580,775Dual deep trenches for high voltage isolation202010,522,663Integrated JFET structure with implanted backgate201910,504,921Integrated circuit with resurf region biasing under buried insulator layers201910,269,895Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect201910,224,402Method of improving lateral BJT characteristics in BCD technology201910,163,680Sinker to buried layer connection region for narrow deep trenches201810,153,269Low dynamic resistance low capacitance diodes201810,079,294Integrated JFET structure with implanted backgate20189,905,428'Split-gate lateral extended drain MOS transistor structure and process'20189,831,135Method of forming a biCMOS semiconductor chip that increases the betas of the bipolar transistors20179,786,665'Dual deep trenches for high voltage isolation'20179,773,777'Low dynamic resistance low capacitance diodes'20179,741,790'Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect'20179,640,611'HV complementary bipolar transistors with lateral collectors on SOI with resurf regions under buried oxide'20179,633,994'BICMOS device having commonly defined gate shield in an ED-CMOS transistor and base in a bipolar transistor'20179,633,995'Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies'20179,595,480'Method of forming a BICMOS semiconductor chip that increases the betas of the bipolar transistors'20179,343,459'Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect'20169,306,013'Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies'20168,878,295'DMOS transistor with a slanted super junction drift structure'20148,648,391'SiGe heterojunction bipolar transistor with an improved breakdown voltage-cutoff frequency product'20148,524,548'DMOS Transistor with a cavity that lies below the drift region'20138,525,233'SiGe heterojunction bipolar transistor with a shallow out-diffused P+ emitter region'20138,298,901'Method for manufacturing bipolar transistors'20128,207,559'Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures'20128,148,799'Self-aligned bipolar transistor structure'20127,867,871'System and method for increasing breakdown voltage of LOCOS isolated devices'20117,714,355'Method of controlling the breakdown voltage of BSCRs and BJT clamps'20107,687,887'Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter'20107,132,342'Method of reducing fringing capacitance in a MOSFET'20066,967,144'Low doped base spacer for reduction of emitter-base capacitance in bipolar transistors with selectively grown epitaxial base'20056,964,907'Method of etching a lateral trench under an extrinsic base and improved bipolar transistor'20056,699,741'Single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region'20046,603,188'Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor'20036,528,862'Bipolar transistor with a box-type germanium profile that lies outside of the emitter-base depletion region'20036,475,848'Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor'20026,380,017'Polysilicon-edge, base-emitter super self-aligned, low-power, high-frequency bipolar transistor and method of forming the transistor'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2014Patents assigned to NAT SEMICONDUCTOR CORP (15)· patent assignee history
2002–2021Based in Sunnyvale, CA, US· patent location history
2012–2021Patents assigned to TEXAS INSTRUMENTS INC (31)· patent assignee history
2012–2014Patents assigned to SADOVNIKOV ALEXEI (7)· patent assignee history
2012–2014Patents assigned to BABCOCK JEFFREY A (3)· patent assignee history
2012Based in San Jose, CA, US· patent location history
2013–2014Patents assigned to BHOLA PUNIT (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 31 | 2012–2021 |
| NAT SEMICONDUCTOR CORP | 15 | 2002–2014 |
| SADOVNIKOV ALEXEIself | 7 | 2012–2014 |
| BABCOCK JEFFREY A | 3 | 2012–2014 |
| BHOLA PUNIT | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 45 | 2002–2021 |
| San Jose, California, US | 1 | 2012 |