Inventor
Shom Ponoth
Inventor
Clifton Park, NY, US
Overview
Patents· 224 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
H10DInorganic electric semiconductor devices26%
H01LSemiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10BElectronic memory devices1%
G01HMeasurement of mechanical vibrations or ultrasonic, sonic or infrasonic waves1%
C23FNon-mechanical removal of metallic material from surface1%
H05KPrinted circuits1%
G06FElectric digital data processing1%
E21BEarth or rock drilling0%
PatentTitleYear
10,838,881Managing connections of input and output devices in a physical room202010,396,070Fin-shaped field effect transistor and capacitor structures201910,312,365Laterally diffused MOSFET on fully depleted SOI having low on-resistance201910,262,992Three dimensional LVDMOS transistor structures201910,236,354Three dimensional monolithic LDMOS transistor201910,192,781Interconnect structures incorporating air gap spacers201910,134,631Size-filtered multimetal structures201810,121,789Self-aligned source/drain contacts201810,115,821FDSOI LDMOS semiconductor device20189,953,978Replacement gate structures for transistor devices20189,941,271Fin-shaped field effect transistor and capacitor structures20189,935,168Gate contact with vertical isolation from source-drain20189,825,141'Three dimensional monolithic LDMOS transistor'20179,799,524'Extended drain MOS device for FDSOI devices'20179,793,378'Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability'20179,768,055'Isolation regions for SOI devices'20179,741,722'Dummy gate structure for electrical isolation of a fin DRAM'20179,711,503'Gate structures with protected end surfaces to eliminate or reduce unwanted EPI material growth'20179,698,148'Reduced footprint LDMOS structure for finFET technologies'20179,673,087'Interconnect structures incorporating air-gap spacers'20179,660,030'Replacement gate electrode with a self-aligned dielectric spacer'20179,633,893'Method to protect against contact related shorts on UTBB'20179,627,377'Self-aligned dielectric isolation for FinFET devices'20179,620,619'Borderless contact structure'20179,613,851'Method for manufacturing interconnect structures incorporating air gap spacers'20179,614,047'Gate contact with vertical isolation from source-drain'20179,595,578'Undercut insulating regions for silicon-on-insulator device'20179,583,613'Metal oxide semiconductor devices and fabrication methods'20179,576,957'Self-aligned source/drain contacts'20179,564,445'Dummy gate structure for electrical isolation of a fin DRAM'20179,558,991'Formation of isolation surrounding well implantation'20179,548,356'Shallow trench isolation structures'20179,515,163'Methods of forming FinFET semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices'20169,508,587'Formation of isolation surrounding well implantation'20169,502,292'Dual shallow trench isolation liner for preventing electrical shorts'20169,484,254'Size-filtered multimetal structures'20169,478,549'FinFET with dielectric isolation by silicon-on-nothing and method of fabrication'20169,472,616'Undercut insulating regions for silicon-on-insulator device'20169,437,504'Method for the formation of fin structures for FinFET devices'20169,418,902'Forming isolated fins from a substrate'20169,406,570'FinFET device'20169,406,548'Formation of isolation surrounding well implantation'20169,406,665'Integrated passive devices for finFET technologies'20169,379,135'FinFET semiconductor device having increased gate height control'20169,379,212'Extended-drain transistor using inner spacer'20169,379,198'Integrated circuit structure having selectively formed metal cap'20169,379,236'LDMOS device and structure for bulk FinFET technology'20169,373,697'Spacer replacement for replacement metal gate semiconductor devices'20169,368,343'Reduced external resistance finFET device'20169,349,838'Semiconductor structure with deep trench thermal conduction'20169,349,598'Gate contact with vertical isolation from source-drain'20169,337,079'Prevention of contact to substrate shorts'20169,334,572'Interconnect structure and method of making same'20169,337,188'Metal-insulator-metal capacitor structure'20169,331,177'Semiconductor structure with deep trench thermal conduction'20169,332,628'Microelectronic structure including air gap'20169,312,143'Formation of isolation surrounding well implantation'20169,312,389'FinFET with undoped body bulk'20169,305,882'Interconnect structures incorporating air-gap spacers'20169,275,911'Hybrid orientation fin field effect transistor and planar field effect transistor'20169,269,792'Method and structure for robust finFET replacement metal gate integration'20169,269,629'Dummy fin formation by gas cluster ion beam'20169,269,621'Dual damascene dual alignment interconnect scheme'20169,269,611'Integrated circuits having gate cap protection and methods of forming the same'20169,263,388'Overlay-tolerant via mask and reactive ion etch (RIE) technique'20169,263,391'Interconnect structures incorporating air-gap spacers'20169,263,290'Sub-lithographic semiconductor structures with non-constant pitch'20169,257,348'Methods of forming replacement gate structures for transistors and the resulting devices'20169,257,350'Manufacturing process for finFET device'20169,252,052'Dual shallow trench isolation liner for preventing electrical shorts'20169,252,242'Semiconductor structure with deep trench thermal conduction'20169,245,965'Uniform finFET gate height'20169,224,654'Fin capacitor employing sidewall image transfer'20159,224,607'Dual epitaxy region integration'20159,219,068'FinFET with dielectric isolation by silicon-on-nothing and method of fabrication'20159,219,153'Methods of forming gate structures for FinFET devices and the resulting semiconductor products'20159,214,378'Undercut insulating regions for silicon-on-insulator device'20159,214,397'Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)'20159,209,202'Enabling bulk FINFET-based devices for FINFET technology with dielectric isolation'20159,202,879'Mask free protection of work function material portions in wide replacement gate electrodes'20159,202,749'Process methods for advanced interconnect patterning'20159,190,313'Shallow trench isolation structures'20159,190,487'Prevention of fin erosion for semiconductor devices'20159,190,465'FinFET device'20159,178,019'Fin isolation in multi-gate field effect transistors'20159,177,820'Sub-lithographic semiconductor structures with non-constant pitch'20159,171,757'Dual shallow trench isolation liner for preventing electrical shorts'20159,171,927'Spacer replacement for replacement metal gate semiconductor devices'20159,165,936'Dummy end-gate based anti-fuse device for finFET technologies'20159,159,653'Copper interconnect structures and methods of making same'20159,147,576'Gate contact with vertical isolation from source-drain'20159,141,749'Interconnect structures and methods for back end of the line integration'20159,105,617'Methods and structures for eliminating or reducing line end epi material growth on gate structures'20159,105,606'Self aligned contact with improved robustness'20159,105,693'Microelectronic structure including air gap'20159,105,641'Profile control in interconnect structures'20159,093,564'Integrated passive devices for FinFET technologies'20159,082,853'Bulk finFET with punchthrough stopper region and method of fabrication'20159,082,873'Method and structure for finFET with finely controlled device width'20159,064,801'Bi-layer gate cap for self-aligned contact formation'20159,059,254'Overlay-tolerant via mask and reactive ion etch (RIE) technique'20159,059,242'FinFET semiconductor device having increased gate height control'20159,059,243'Shallow trench isolation structures'20159,059,270'Replacement gate MOSFET with raised source and drain'20159,059,251'Microelectronic structure including air gap'20159,041,116'Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)'20159,034,703'Self aligned contact with improved robustness'20158,999,774'Bulk fin-field effect transistors with well defined isolation'20158,999,799'Maskless dual silicide contact formation'20159,000,522'FinFET with dielectric isolation by silicon-on-nothing and method of fabrication'20158,993,382'Bulk fin-field effect transistors with well defined isolation'20158,987,790'Fin isolation in multi-gate field effect transistors'20158,987,837'Stress enhanced finFET devices'20158,987,070'SOI device with embedded liner in box layer to limit STI recess'20158,946,908'Dual-metal self-aligned wires and vias'20158,946,792'Dummy fin formation by gas cluster ion beam'20158,946,006'Replacement gate MOSFET with raised source and drain'20158,941,179'Finfets and fin isolation structures'20158,941,156'Self-aligned dielectric isolation for FinFET devices'20158,937,359'Contact formation for ultra-scaled devices'20158,932,918'FinFET with self-aligned punchthrough stopper'20158,928,067'Bulk fin-field effect transistors with well defined isolation'20158,912,627'Electrical fuse structure and method of fabricating same'20148,907,458'Creation of vias and trenches with different depths'20148,906,807'Single fin cut employing angled processing methods'20148,901,744'Hybrid copper interconnect structure and method of fabricating same'20148,896,067'Method of forming finFET of variable channel width'20148,883,623'Facilitating gate height uniformity and inter-layer dielectric protection'20148,877,645'Integrated circuit structure having selectively formed metal cap'20148,871,624'Sealed air gap for semiconductor chip'20148,859,379'Stress enhanced finFET devices'20148,853,076'Self-aligned contacts'20148,835,305'Method of fabricating a profile control in interconnect structures'20148,836,031'Electrical isolation structures for ultra-thin semiconductor-on-insulator devices'20148,835,244'Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes'20148,828,862'Air-dielectric for subtractive etch line and via metallization'20148,828,828'MOSFET including asymmetric source and drain regions'20148,829,617'Uniform finFET gate height'20148,828,876'Dual mandrel sidewall image transfer processes'20148,809,920'Prevention of fin erosion for semiconductor devices'20148,809,183'Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer'20148,803,318'Semiconductor chips including passivation layer trench structure'20148,803,321'Dual damascene dual alignment interconnect scheme'20148,802,558'Copper interconnect structures and methods of making same'20148,796,783'Borderless contact structure employing dual etch stop layers'20148,785,284'FinFETs and fin isolation structures'20148,772,933'Interconnect structure and method of making same'20148,772,180'Interconnect structure and method of making same'20148,772,874'MOSFET including asymmetric source and drain regions'20148,765,585'Method of forming a borderless contact structure employing dual etch stop layers'20148,754,520'Formation of air gap with protection of metal lines'20148,754,483'Low-profile local interconnect and method of making the same'20148,735,279'Air-dielectric for subtractive etch line and via metallization'20148,716,127'Metal alloy cap integration'20148,704,343'Borderless interconnect line structure self-aligned to upper and lower level contact vias'20148,703,550'Dual shallow trench isolation liner for preventing electrical shorts'20148,703,553'MOS capacitors with a finFET process'20148,703,604'Creation of vias and trenches with different depths'20148,673,738'Shallow trench isolation structures'20148,637,400'Interconnect structures and methods for back end of the line integration'20148,637,381'High-k dielectric and silicon nitride box region'20148,629,511'Mask free protection of work function material portions in wide replacement gate electrodes'20148,629,008'Electrical isolation structures for ultra-thin semiconductor-on-insulator devices'20148,623,712'Bulk fin-field effect transistors with well defined isolation'20148,609,534'Electrical fuse structure and method of fabricating same'20138,604,539'Bulk fin-field effect transistors with well defined isolation'20138,592,290'Cut-very-last dual-EPI flow'20138,592,263'FinFET diode with increased junction area'20138,581,320'MOS capacitors with a finfet process'20138,569,125'FinFET with improved gate planarity'20138,569,152'Cut-very-last dual-epi flow'20138,569,168'Dual-metal self-aligned wires and vias'20138,558,284'Integrated circuit line with electromigration barriers'20138,525,339'Hybrid copper interconnect structure and method of fabricating same'20138,518,773'Method of fabricating semiconductor capacitor'20138,492,270'Structure for nano-scale metallization and method for fabricating same'20138,492,274'Metal alloy cap integration'20138,492,265'Pad bonding employing a self-aligned plated liner for adhesion enhancement'20138,482,132'Pad bonding employing a self-aligned plated liner for adhesion enhancement'20138,476,160'Sublithographic patterning employing image transfer of a controllably damaged dielectric sidewall'20138,440,505'Semiconductor chips including passivation layer trench structure'20138,432,002'Method and structure for low resistive source and drain regions in a replacement metal gate process flow'20138,420,459'Bulk fin-field effect transistors with well defined isolation'20138,421,239'Crenulated wiring structure and method for integrated circuit interconnects'20138,404,582'Structure and method for manufacturing interconnect structures having self-aligned dielectric caps'20138,399,350'Formation of air gap with protection of metal lines'20138,390,079'Sealed air gap for semiconductor chip'20138,383,507'Method for fabricating air gap interconnect structures'20138,354,703'Semiconductor capacitor'20138,354,751'Interconnect structure for electromigration enhancement'20138,349,674'Forming borderless contact for transistors in a replacement metal gate process'20138,299,625'Borderless interconnect line structure self-aligned to upper and lower level contact vias'20128,288,268'Microelectronic structure including air gap'20128,232,195'Method for fabricating back end of the line structures with liner and seed materials'20128,232,204'Method of forming borderless contact for transistor'20128,232,618'Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach'20128,227,339'Creation of vias and trenches with different depths'20128,211,776'Integrated circuit line with electromigration barriers'20128,120,179'Air gap interconnect structures and methods for forming the same'20128,030,202'Temporary etchable liner for forming air gap'20118,021,974'Structure and method for back end of the line integration'20118,008,669'Programmable anti-fuse structure with DLC dielectric layer'20118,003,524'Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement'20118,003,520'Air gap structure having protective metal silicide pads on a metal feature'20117,977,032'Method to create region specific exposure in a layer'20117,960,276'Conductor-dielectric structure and method for fabricating'20117,952,146'Grain growth promotion layer for semiconductor interconnect structures'20117,943,480'Sub-lithographic dimensioned air gap formation and related structure'20117,928,570'Interconnect structure'20117,892,968'Via gouging methods and related semiconductor structure'20117,888,252'Self-aligned contact'20117,884,477'Air gap structure having protective metal silicide pads on a metal feature'20117,790,601'Forming interconnects with air gaps'20107,709,344'Integrated circuit fabrication process using gas cluster ion beam etching'20107,687,877'Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same'20107,670,497'Oxidant and passivant composition and method for use in treating a microelectronic structure'20107,666,787'Grain growth promotion layer for semiconductor interconnect structures'20107,531,444'Method to create air gaps using non-plasma processes to damage ILD materials'20097,498,254'Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement'20097,402,883'Back end of the line structures with liner and noble metal layer'20087,341,948'Method of making a semiconductor structure with a plating enhancement layer'20087,253,098'Maintaining uniform CMP hard mask thickness'20077,215,006'Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement'20076,832,036'Siloxane optical waveguides'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2019Patents assigned to IBM (186)· patent assignee history
2007–2013Based in Fishkill, NY, US· patent location history
2010–2017Based in Clifton Park, NY, US· patent location history
2010–2015Based in Albany, NY, US· patent location history
2012–2017Patents assigned to PONOTH SHOM (68)· patent assignee history
2012–2017Patents assigned to HORAK DAVID V (37)· patent assignee history
2012–2017Patents assigned to YANG CHIH-CHAO (33)· patent assignee history
2014–2018Patents assigned to GLOBALFOUNDRIES INC (45)· patent assignee history
2014–2018Based in Gaithersburg, MD, US· patent location history
2014–2018Based in Los Angeles, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 186 | 2007–2019 |
| PONOTH SHOMself | 68 | 2012–2017 |
| GLOBALFOUNDRIES INC | 45 | 2014–2018 |
| HORAK DAVID V | 37 | 2012–2017 |
| YANG CHIH-CHAO | 33 | 2012–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Clifton Park, New York, US | 105 | 2010–2017 |
| Gaithersburg, Maryland, US | 43 | 2014–2018 |
| Los Angeles, California, US | 16 | 2014–2018 |
| Albany, New York, US | 15 | 2010–2015 |
| Fishkill, New York, US | 14 | 2007–2013 |