Inventor
Xiaowei Deng
Inventor
Plano, TX, US
Overview
Patents· 53 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores59%
H10BElectronic memory devices9%
H03KPulse technique8%
H10DInorganic electric semiconductor devices8%
G06FElectric digital data processing4%
G01RMeasuring electric variables3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
Y02PClimate change mitigation technologies in the production or processing of goods3%
B82YSpecific uses or applications of nanostructures1%
LOC181%
PatentTitleYear
D0930072Label tape cassette20219,805,788'Array power supply-based screening of static random access memory cells for bias temperature instability'20179,576,643'Array power supply-based screening of static random access memory cells for bias temperature instability'20179,472,268'SRAM with buffered-read bit cells and its testing'20169,466,356'Array power supply-based screening of static random access memory cells for bias temperature instability'20169,455,021'Array power supply-based screening of static random access memory cells for bias temperature instability'20169,412,437'SRAM with buffered-read bit cells and its testing'20169,208,899'Universal test structures based SRAM on-chip parametric test module and methods of operating and testing'20159,208,902'Bitline leakage detection in memories'20159,208,832'Functional screening of static random access memories using an array bias voltage'20158,760,927'Efficient static random-access memory layout'20148,716,808'Static random-access memory cell array with deep well regions'20148,670,265'Reducing power in SRAM using supply voltage control'20148,654,575'Disturb-free static random access memory cell'20148,654,562'Static random access memory cell with single-sided buffer and asymmetric construction'20148,498,143'Solid-state memory cell with improved read stability'20138,472,228'Array-based integrated circuit with reduced proximity effects'20138,472,229'Array-based integrated circuit with reduced proximity effects'20138,462,542'Bit-by-bit write assist for solid-state memory'20138,437,213'Characterization of bits in a functional memory'20138,432,760'Method of screening static random access memories for unstable memory cells'20138,379,467'Structure and methods for measuring margins in an SRAM bit'20138,305,798'Memory cell with equalization write assist in solid-state memory'20128,233,341'Method and structure for SRAM cell trip voltage measurement'20128,228,749'Margin testing of static random access memory cells'20128,174,914'Method and structure for SRAM Vmin/Vmax measurement'20128,139,431'Structure and methods for measuring margins in an SRAM bit'20128,064,279'Structure and method for screening SRAMS'20117,936,623'Universal structure for memory cell characterization'20117,924,640'Method for memory cell characterization using universal structure'20117,855,907'Mitigation of charge sharing in memory devices'20107,821,816'Method for constructing Shmoo plots for SRAMs'20107,816,740'Memory cell layout structure with outer bitline'20107,499,354'Method for testing transistors having an active region that is common with other transistors and a testing circuit for accomplishing the same'20097,301,849'System for reducing row periphery power consumption in memory devices'20077,298,663'Bit line control for low power in standby'20077,164,596'SRAM cell with column select line'20077,120,082'System for reducing row periphery power consumption in memory devices'20067,061,820'Voltage keeping scheme for low-leakage memory devices'20067,039,818'Low leakage SRAM scheme'20067,027,346'Bit line control for low power in standby'20066,975,143'Static logic design for CMOS'20056,956,398'Leakage current reduction method'20056,925,025'SRAM device and a method of powering-down the same'20056,922,370'High performance SRAM device and method of powering-down the same'20056,870,375'System and method for measuring a capacitance associated with an integrated circuit'20056,801,057'Silicon-on-insulator dynamic logic'20046,731,533'Loadless 4T SRAM cell with PMOS drivers'20046,573,549'Dynamic threshold voltage 6T SRAM cell'20036,552,566'Logic array circuits using silicon-on-insulator logic'20036,539,526'Method and apparatus for determining capacitances for a device within an integrated circuit'20036,486,707'CMOS pass transistor logic circuitry using quantum mechanical tunneling structures'20026,362,660'CMOS latch and register circuitry using quantum mechanical tunneling structures'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2017Patents assigned to TEXAS INSTRUMENTS INC (52)· patent assignee history
2002–2017Based in Plano, TX, US· patent location history
2011–2016Patents assigned to DENG XIAOWEI (20)· patent assignee history
2011–2013Patents assigned to HOUSTON THEODORE W (4)· patent assignee history
2012–2016Patents assigned to LOH WAH KIT (11)· patent assignee history
2013–2015Patents assigned to LOH WAH K (2)· patent assignee history
2021Based in Zhuhai, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 52 | 2002–2017 |
| DENG XIAOWEIself | 20 | 2011–2016 |
| LOH WAH KIT | 11 | 2012–2016 |
| HOUSTON THEODORE W | 4 | 2011–2013 |
| LOH WAH K | 2 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Plano, Texas, US | 52 | 2002–2017 |
| Zhuhai, CN | 1 | 2021 |