Inventor
Marco Fontana
Inventor
Milan, IT
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores63%
G06FElectric digital data processing11%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems7%
D06NWall, floor, or like covering materials, e.g. linoleum, oilcloth, artificial leather, roofing felt, consisting of a fibrous web coated with a layer of macromolecular material4%
G05FSystems for regulating electric or magnetic variables4%
H03KPulse technique4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
Y10TTechnical subjects covered by former us classification4%
PatentTitleYear
9,830,087Memory wear leveling20179,747,045'Sub-sector wear leveling in memories'20179,275,708'Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information'20169,195,590'Sub-sector wear leveling in memories'20158,681,572'Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information'20147,706,160'High voltage generator of the DAC-controlled type'20106,605,985'High-efficiency power charge pump supplying high DC output currents'20036,477,625'Method and system for reading a memory by applying control signals thereto'20026,438,669'Timesharing internal bus, particularly for non-volatile memories'20026,175,521'Voltage regulator for programming electrically programmable non-volatile memory cells in a cell matrix'20016,148,413'Memory under test programming and reading device'20006,075,718'Method and device for reading a non-erasable memory cell'20006,009,041'Method and circuit for trimming the internal timing conditions of a semiconductor memory device'19995,982,677'Compensated voltage regulator'19995,959,902'Voltage level shifter device, particulary for a nonvolatile memory'19995,841,728'Hierarchic memory device having auxiliary lines connected to word lines'19985,821,788'Zero consumption power-on-reset'19985,815,437'Data input/output managing device, particularly for a non-volatile memory'19985,754,483'Reference word line and data propagation reproduction circuit for memories provided with hierarchical decoders'19985,708,604'Dynamic selection control in a memory'19985,659,498'Unbalanced latch and fuse circuit including the same'19973,962,512'Composite laminar structure and relative manufacturing process'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976–2017Based in Milan, IT· patent location history
1997–2002Patents assigned to SGS THOMSON MICROELECTRONICS (10)· patent assignee history
1999–2003Patents assigned to ST MICROELECTRONICS SRL (4)· patent assignee history
2010Patents assigned to BITONTI DAVIDE (1)· patent assignee history
2010Based in Milano, IT· patent location history
2014–2017Patents assigned to MICRON TECHNOLOGY INC (5)· patent assignee history
2014Patents assigned to BOLOGNINI GIOVANNI (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SGS THOMSON MICROELECTRONICS | 10 | 1997–2002 |
| MICRON TECHNOLOGY INC | 5 | 2014–2017 |
| ST MICROELECTRONICS SRL | 4 | 1999–2003 |
| BITONTI DAVIDE | 1 | 2010 |
| BOLOGNINI GIOVANNI | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Milan, IT | 21 | 1976–2017 |
| Milano, IT | 1 | 2010 |