LexDanaLexDanabeta
Inventor

Paul Serris

Inventor
Sunnyvale, CA, US

Overview

26→
Patents
2002–2020
Patent span
Physics
Primary field (CPC G)

Patents· 26 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
10,628,160Selective poisoning of data during runahead202010,001,996Selective poisoning of data during runahead20189,891,972'Lazy runahead operation for a microprocessor'20189,875,105Checkpointed buffer for re-entry from runahead20189,823,931'Queued instruction re-dispatch after runahead'20179,740,553'Managing potentially invalid results during runahead'20179,645,929'Speculative permission acquisition for shared memory'20179,632,976'Lazy runahead operation for a microprocessor'20179,081,563'Method and apparatus for enhancing scheduling in an advanced microprocessor'20158,516,224'Pipeline replay support for multicycle operations'20138,209,517'Method and apparatus for enhancing scheduling in an advanced microprocessor'20128,117,423'Pipeline replay support for multicycle operations'20127,886,135'Pipeline replay support for unaligned memory operations'20117,873,793'Supporting speculative modification in a data cache'20117,725,656'Braided set associative caching techniques'20107,685,403'Pipeline replay support for multi-cycle operations'20107,606,979'Method and system for conservatively managing store capacity available to a processor issuing stores'20097,225,299'Supporting speculative modification in a data cache'20077,149,851'Method and system for conservatively managing store capacity available to a processor issuing stores'20067,134,001'Pipeline replay support for unaligned memory operations'20067,089,404'Method and apparatus for enhancing scheduling in an advanced microprocessor'20066,728,865'Pipeline replay support for unaligned memory operations'20046,604,188'Pipeline replay support for multi-cycle operations wherein all VLIW instructions are flushed upon detection of a multi-cycle atom operation in a VLIW instruction'20036,571,316'Cache memory array for multiple address spaces'20036,513,110'Check instruction and method'20036,363,336'Fine grain translation discrimination'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2007Patents assigned to TRANSMETA CORP (9)· patent assignee history
2002–2015Based in Sunnyvale, CA, US· patent location history
2006–2020Based in San Jose, CA, US· patent location history
2009–2018Patents assigned to SERRIS PAUL (9)· patent assignee history
2010–2013Patents assigned to COON BRETT (4)· patent assignee history
2010–2013Patents assigned to D SOUZA GODFREY (4)· patent assignee history
2011Based in Sunnyavle, CA, US· patent location history
2017–2020Patents assigned to NVIDIA CORP (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SERRIS PAULself92009–2018
TRANSMETA CORP92002–2007
NVIDIA CORP82017–2020
COON BRETT42010–2013
D SOUZA GODFREY42010–2013
Locations
LocationPatentsSpan
Sunnyvale, California, US152002–2015
San Jose, California, US102006–2020
Sunnyavle, California, US12011