Inventor
Poovaiah M. Palangappa
Inventor
San Jose, CA, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing42%
H03MCoding42%
G05BControl or regulating systems in general8%
G11CStatic stores8%
PatentTitleYear
11,088,707Low density parity check (LDPC) decoder architecture with check node storage (CNS) or bounded circulant202111,063,607Compressing error vectors for decoding logic to store compressed in a decoder memory used by the decoding logic202110,944,428Device, system and method for determining bit reliability information202110,707,901Die-wise residual bit error rate (RBER) estimation for memories202010,547,327Self-configuring error control coding202010,372,620Devices, systems, and methods having high data deduplication and low read latencies2019Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2019–2021Patents assigned to INTEL CORP (6)· patent assignee history
2019–2020Based in Santa Clara, CA, US· patent location history
2020–2021Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 6 | 2019–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 4 | 2020–2021 |
| Santa Clara, California, US | 2 | 2019–2020 |