Inventor

Basab Bandyopadhyay

Inventor

Austin, TX, US

Overview

1997–2004

Patent span

Electricity

Primary field (CPC H)

Patents· 56 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1067%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

H10DInorganic electric semiconductor devices4%

H10BElectronic memory devices3%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

PatentTitleYear

6,720,227'Method of forming source/drain regions in a semiconductor device'2004 6,599,810'Shallow trench isolation formation with ion implantation'2003 6,380,047'Shallow trench isolation formation with two source/drain masks and simplified planarization mask'2002 6,376,330'Dielectric having an air gap formed between closely spaced interconnect lines'2002 6,353,253'Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization'2002 6,326,298'Substantially planar semiconductor topography using dielectrics and chemical mechanical polish'2001 6,309,947'Method of manufacturing a semiconductor device with improved isolation region to active region topography'2001 6,208,015'Interlevel dielectric with air gaps to lessen capacitive coupling'2001 6,171,962'Shallow trench isolation formation without planarization mask'2001 6,165,906'Semiconductor topography employing a shallow trench isolation structure with an improved trench edge'2000 6,162,699'Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery'2000 6,153,833'Integrated circuit having interconnect lines separated by a dielectric having a capping layer'2000 6,150,721'Integrated circuit which uses a damascene process for producing staggered interconnect lines'2000 6,143,624'Shallow trench isolation formation with spacer-assisted ion implantation'2000 6,130,467'Shallow trench isolation with spacers for improved gate oxide quality'2000 6,127,264'Integrated circuit having conductors of enhanced cross-sectional area'2000 6,127,719'Subfield conductive layer and method of manufacture'2000 6,124,183'Shallow trench isolation formation with simplified reverse planarization mask'2000 6,091,149'Dissolvable dielectric method and structure'2000 6,090,712'Shallow trench isolation formation with no polish stop'2000 6,090,703'Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer'2000 6,074,927'Shallow trench isolation formation with trench wall spacer'2000 6,049,134'Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization'2000 6,037,671'Stepper alignment mark structure for maintaining alignment integrity'2000 6,031,289'Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines'2000 5,998,293'Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect'1999 5,970,363'Shallow trench isolation formation with improved trench edge oxide'1999 5,968,843'Method of planarizing a semiconductor topography using multiple polish pads'1999 5,970,362'Simplified shallow trench isolation formation with no polish stop'1999 5,953,626'Dissolvable dielectric method'1999 5,930,645'Shallow trench isolation formation with reduced polish stop thickness'1999 5,926,717'Method of making an integrated circuit with oxidizable trench liner'1999 5,926,713'Method for achieving global planarization by forming minimum mesas in large field areas'1999 5,924,008'Integrated circuit having local interconnect for reducing signal cross coupled noise'1999 5,899,727'Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization'1999 5,894,168'Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization'1999 5,854,515'Integrated circuit having conductors of enhanced cross-sectional area'1998 5,854,131'Integrated circuit having horizontally and vertically offset interconnect lines'1998 5,851,913'Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process'1998 5,850,105'Substantially planar semiconductor topography using dielectrics and chemical mechanical polish'1998 5,847,462'Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer'1998 5,846,876'Integrated circuit which uses a damascene process for producing staggered interconnect lines'1998 5,830,773'Method for forming semiconductor field region dielectrics having globally planarized upper surfaces'1998 5,827,776'Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines'1998 5,814,555'Interlevel dielectric with air gaps to lessen capacitive coupling'1998 5,811,334'Wafer cleaning procedure useful in the manufacture of a non-volatile memory device'1998 5,792,706'Interlevel dielectric with air gaps to reduce permitivity'1998 5,783,864'Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect'1998 5,783,481'Semiconductor interlevel dielectric having a polymide for producing air gaps'1998 5,767,012'Method of forming a recessed interconnect structure'1998 5,767,000'Method of manufacturing subfield conductive layer'1998 5,766,803'Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization'1998 5,759,913'Method of formation of an air gap within a semiconductor dielectric by solvent desorption'1998 5,733,798'Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization'1998 5,717,242'Integrated circuit having local interconnect for reduing signal cross coupled noise'1998 5,679,605'Multilevel interconnect structure of an integrated circuit formed by a single via etch and dual fill process'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2004Patents assigned to ADVANCED MICRO DEVICES INC (55)· patent assignee history

1997–2004Based in Austin, TX, US· patent location history

1999Patents assigned to ADVANCED MICRO DEVCIES INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	55	1997–2004
ADVANCED MICRO DEVCIES INC	1	1999

Locations

Location	Patents	Span
Austin, Texas, US	56	1997–2004