Inventor
Hwa-Sung Rhee
Inventor
Seongnam-si, KR
Overview
Patents· 70 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices42%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H01LSemiconductor devices9%
H10BElectronic memory devices3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G01RMeasuring electric variables2%
A61BDiagnosis1%
B65DContainers for storage or transport of articles or materials, e.g. bags, barrels, bottles, boxes, cans, cartons, crates, drums, jars, tanks, hoppers, forwarding containers1%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
10,622,265Method of detecting failure of a semiconductor device202010,600,702Test element group and semiconductor wafer including the same202010,522,430Semiconductor device201910,410,871Semiconductor devices and methods of manufacturing the same201910,276,567Semiconductor device201910,074,572Integrated circuit devices and methods of manufacturing the same201810,032,886Semiconductor device20189,984,886Semiconductor devices and methods of manufacturing the same20189,922,979'Integrated circuit device and method of manufacturing the same'20189,754,789'Method of fabricating semiconductor device and computing system for implementing the method'20179,673,330'Integrated circuit devices and methods of manufacturing the same'20179,496,192'Test pattern of semiconductor device'20169,412,693'Semiconductor device having jumper pattern and blocking pattern'20169,318,573'Field effect transistor having germanium nanorod and method of manufacturing the same'20169,190,402'Semiconductor device comprising capacitor and method of manufacturing the same'20158,445,968'Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same'20138,426,916'Semiconductor integrated circuit devices having different thickness silicon-germanium layers'20138,338,261'Semiconductor device including field effect transistor and method of forming the same'20128,232,613'Germanium silicide layer including vanadium, platinum, and nickel'20128,207,033'Methods of fabricating different thickness silicon-germanium layers on semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby'20127,981,750'Methods of fabrication of channel-stressed semiconductor devices'20117,952,147'Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same'20117,879,668'Method of manufacturing a semiconductor device'20117,863,142'Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device'20117,791,146'Semiconductor device including field effect transistor and method of forming the same'20107,776,723'Method of manufacturing an epitaxial semiconductor substrate and method of manufacturing a semiconductor device'20107,728,393'Semiconductor device'20107,723,193'Method of forming an at least penta-sided-channel type of FinFET transistor'20107,714,394'CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same'20107,671,420'Semiconductor devices having faceted channels and methods of fabricating such devices'20107,642,140'CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same'20107,619,285'Method of fabricating CMOS transistor and CMOS transistor fabricated thereby'20097,611,951'Method of fabricating MOS transistor having epitaxial region'20097,611,973'Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same'20097,601,983'Transistor and method of manufacturing the same'20097,582,535'Method of forming MOS transistor having fully silicided metal gate electrode'20097,576,395'Dual gate stack CMOS structure with different dielectrics'20097,439,596'Transistors for semiconductor device and methods of fabricating the same'20087,385,247'At least penta-sided-channel type of FinFET transistor'20087,368,792'MOS transistor with elevated source/drain structure'20087,365,010'Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same'20087,361,563'Methods of fabricating a semiconductor device using a selective epitaxial growth technique'20087,354,835'Method of fabricating CMOS transistor and CMOS transistor fabricated thereby'20087,307,274'Transistors having reinforcement layer patterns and methods of forming the same'20077,250,655'MOS transistor having a T-shaped gate electrode'20077,195,987'Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein'20077,183,172'Method of forming silicon-on-insulator (SOI) semiconductor substrate and SOI semiconductor substrate formed thereby'20077,101,776'Method of fabricating MOS transistor using total gate silicidation process'20067,084,041'Bipolar device and method of manufacturing the same including pre-treatment using germane gas'20067,033,895'Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process'20066,987,310'Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device'20066,917,085'Semiconductor transistor using L-shaped spacer'20056,914,301'CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same'20056,884,705'Semiconductor device having hetero grain stack gate and method of forming the same'20056,881,621'Method of fabricating SOI substrate having an etch stop layer, and method of fabricating SOI integrated circuit using the same'20056,881,650'Method for forming SOI substrate'20056,878,580'Semiconductor device having gate with negative slope and method for manufacturing the same'20056,815,320'Method for fabricating semiconductor device including gate spacer'20046,806,517'Flash memory having local SONOS structure using notched gate and manufacturing method thereof'20046,794,306'Semiconductor device having gate all around type transistor and method of forming the same'20046,750,532'CMOS semiconductor device and method of manufacturing the same'20046,716,689'MOS transistor having a T-shaped gate electrode and method for fabricating the same'20046,696,328'CMOS gate electrode using selective growth and a fabrication method thereof'20046,693,013'Semiconductor transistor using L-shaped spacer and method of fabricating the same'20046,670,677'SOI substrate having an etch stop layer and an SOI integrated circuit fabricated thereon'20036,667,525'Semiconductor device having hetero grain stack gate'20036,633,066'CMOS integrated circuit devices and substrates having unstrained silicon active layers'20036,605,847'Semiconductor device having gate all around type transistor and method of forming the same'20036,524,902'Method of manufacturing CMOS semiconductor device'20036,518,645'SOI-type semiconductor device and method of forming the same'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2020Patents assigned to SAMSUNG ELECTRONICS CO LTD (70)· patent assignee history
2003–2010Based in Seoul, KR· patent location history
2006–2020Based in Seongnam-si, KR· patent location history
2006–2008Based in Yongin-si, KR· patent location history
2008–2013Based in Gyeonggi-do, KR· patent location history
2010Based in Sungnam, KR· patent location history
2012–2017Patents assigned to RHEE HWA-SUNG (7)· patent assignee history
2012–2013Patents assigned to LEE HO (4)· patent assignee history
2012–2013Patents assigned to KIM MYUNG-SUN (3)· patent assignee history
2012–2013Patents assigned to YI JI-HYE (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 70 | 2003–2020 |
| RHEE HWA-SUNGself | 7 | 2012–2017 |
| LEE HO | 4 | 2012–2013 |
| KIM MYUNG-SUN | 3 | 2012–2013 |
| YI JI-HYE | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Seongnam-si, KR | 38 | 2006–2020 |
| Seoul, KR | 22 | 2003–2010 |
| Gyeonggi-do, KR | 5 | 2008–2013 |
| Yongin-si, KR | 2 | 2006–2008 |
| Sungnam, KR | 1 | 2010 |