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Inventor

Junjing Bao

Inventor
San Diego, CA, US

Overview

58→
Patents
2012–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 58 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H01LSemiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10DInorganic electric semiconductor devices8%
B82YSpecific uses or applications of nanostructures2%
H01HElectric switches2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
H10BElectronic memory devices2%
B33YAdditive manufacturing, i.e. manufacturing of three-dimensional [3d] objects by additive deposition, additive agglomeration or additive layering, e.g. by 3d printing, stereolithography or selective laser sintering1%
G05BControl or regulating systems in general1%
PatentTitleYear
10,847,507Contact liner to enable different CPP devices202010,833,017Contact for semiconductor device202010,686,031Finger metal-oxide-metal (FMOM) capacitor202010,665,678Transistor with fluorinated graphene spacer202010,651,122Integrated circuit (IC) interconnect structure having a metal layer with asymmetric metal line-dielectric structures supporting self-aligned vertical interconnect accesses (VIAS)202010,636,737Structure and method of metal wraparound for low via resistance202010,636,789Transistor with low resistivity carbon alloy202010,615,113Rotated metal-oxide-metal (RTMOM) capacitor202010,566,413MIM capacitor containing negative capacitance material202010,354,955Graphene as interlayer dielectric201910,347,821Electrode structure for resistive memory device201910,325,979High density and reliable vertical natural capacitors201910,263,080Transistor with fluorinated graphene spacer201910,186,482Self aligned via fuse201910,177,031Subtractive etch interconnects201910,062,763Method and apparatus for selectively forming nitride caps on metal gate201810,049,926Metal lines having etch-bias independent height201810,043,796Vertically stacked nanowire field effect transistors20189,953,979Contact wrap around structure20189,893,011'Back-end electrically programmable fuse'20189,865,798'Electrode structure for resistive memory device'20189,799,560'Self-aligned structure'20179,793,164'Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices'20179,721,891'Integrated circuit devices and methods'20179,685,404'Back-end electrically programmable fuse'20179,559,051'Method for manufacturing in a semiconductor device a low resistance via without a bottom liner'20179,543,248'Integrated circuit devices and methods'20179,536,830'High performance refractory metal / copper interconnects to eliminate electromigration'20179,536,842'Structure with air gap crack stop'20179,455,186'Selective local metal cap layer formation for improved electromigration behavior'20169,431,346'Graphene-metal E-fuse'20169,425,144'Metal fuse structure for improved programming capability'20169,412,654'Graphene sacrificial deposition layer on beol copper liner-seed for mitigating queue-time issues between liner and plating step'20169,406,560'Selective local metal cap layer formation for improved electromigration behavior'20169,385,038'Selective local metal cap layer formation for improved electromigration behavior'20169,337,082'Metal lines having etch-bias independent height'20169,324,635'Semiconductor interconnect structure having a graphene-based barrier metal layer'20169,324,634'Semiconductor interconnect structure having a graphene-based barrier metal layer'20169,324,655'Modified via bottom for beol via efuse'20169,293,412'Graphene and metal interconnects with reduced contact resistance'20169,257,391'Hybrid graphene-metal interconnect structures'20169,240,376'Self-aligned via fuse'20169,202,743'Graphene and metal interconnects'20159,171,801'E-fuse with hybrid metallization'20159,105,638'Via-fuse with low dielectric constant'20159,099,468'Electronic fuse vias in interconnect structures'20159,093,452'Electronic fuse with resistive heater'20159,076,847'Selective local metal cap layer formation for improved electromigration behavior'20159,064,871'Vertical electronic fuse'20159,059,170'Electronic fuse having a damaged region'20159,034,664'Method to resolve hollow metal defects in interconnects'20158,962,467'Metal fuse structure for improved programming capability'20158,921,167'Modified via bottom for BEOL via efuse'20148,916,461'Electronic fuse vias in interconnect structures'20148,841,208'Method of forming vertical electronic fuse interconnect structures including a conductive cap'20148,736,020'Electronic anti-fuse'20148,384,219'Semiconductor having interconnects with improved mechanical properties by insertion of nanoparticles'20138,129,269'Method of improving mechanical properties of semiconductor interconnects with nanoparticles'2012

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2012–2019Patents assigned to IBM (28)· patent assignee history
2012–2017Patents assigned to BAO JUNJING (8)· patent assignee history
2012–2017Based in Fishkill, NY, US· patent location history
2014–2017Patents assigned to BONILLA GRISELDA (4)· patent assignee history
2014–2017Based in Cedar Grove, NJ, US· patent location history
2015–2020Based in San Diego, CA, US· patent location history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (11)· patent assignee history
2017–2020Patents assigned to QUALCOMM INC (21)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM282012–2019
QUALCOMM INC212017–2020
GLOBALFOUNDRIES INC112016–2019
BAO JUNJINGself82012–2017
BONILLA GRISELDA42014–2017
Locations
LocationPatentsSpan
San Diego, California, US362015–2020
Cedar Grove, New Jersey, US142014–2017
Fishkill, New York, US82012–2017