Inventor
John R. Goss
Inventor
South Burlington, VT, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables32%
G06FElectric digital data processing26%
G11CStatic stores26%
A01HNew plants or non-transgenic processes for obtaining them3%
A01NPreservation of bodies of humans or animals or plants or parts thereof3%
H01LSemiconductor devices3%
H03KPulse technique3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
PatentTitleYear
10,971,243Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register202110,955,474Customer-transparent logic redundancy for improved yield202110,692,584Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register202010,553,302Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register202010,551,436Customer-transparent logic redundancy for improved yield20209,881,694'Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register'20189,791,507'Customer-transparent logic redundancy for improved yield'20179,760,673'Application specific integrated circuit (ASIC) test screens and selection of such screens'20179,653,330'Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning'20179,274,171'Customer-transparent logic redundancy for improved yield'20168,963,566'Thermally adaptive in-system allocation'20158,949,767'Reliability evaluation and system fail warning methods using on chip parametric monitors'20158,570,820'Selectable repair pass masking'20138,504,975'Reliability evaluation and system fail warning methods using on chip parametric monitors'20138,095,907'Reliability evaluation and system fail warning methods using on chip parametric monitors'20127,916,826'Diagnostic method and apparatus for non-destructively observing latch data'20117,911,820'Regulating electrical fuse programming current'20117,904,839'System and method for controlling access to addressable integrated circuits'20117,831,936'Structure for a system for controlling access to addressable integrated circuits'20107,656,182'Testing method using a scalable parametric measurement macro'20107,560,946'Method of acceptance for semiconductor devices'20097,487,477'Parametric-based semiconductor design'20097,453,973'Diagnostic method and apparatus for non-destructively observing latch data'20087,145,977'Diagnostic method and apparatus for non-destructively observing latch data'20065,006,154'Method of synchronizing flowering in plants'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991Based in Modesto, CA, US· patent location history
2006–2021Patents assigned to IBM (20)· patent assignee history
2006–2021Based in South Burlington, VT, US· patent location history
2012–2013Patents assigned to BICKFORD JEANNE P (2)· patent assignee history
2012–2013Patents assigned to GOSS JOHN R (2)· patent assignee history
2012–2013Patents assigned to HABIB NAZMUL (2)· patent assignee history
2017Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
2017Based in St. Albans, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 20 | 2006–2021 |
| BICKFORD JEANNE P | 2 | 2012–2013 |
| GLOBALFOUNDRIES INC | 2 | 2017 |
| GOSS JOHN Rself | 2 | 2012–2013 |
| HABIB NAZMUL | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 22 | 2006–2021 |
| St. Albans, VT, US | 2 | 2017 |
| Modesto, California, US | 1 | 1991 |