LexDanaLexDanabeta
Inventor

Igor Arsovski

Inventor
Williston, VT, US

Overview

105→
Patents
2006–2021
Patent span
Physics
Primary field (CPC G)

Patents· 105 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores46%
G06FElectric digital data processing22%
H03KPulse technique9%
G01RMeasuring electric variables7%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
H01LSemiconductor devices2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H04BTransmission1%
G05DSystems for controlling or regulating non-electric variables1%
G05FSystems for regulating electric or magnetic variables1%
PatentTitleYear
11,114,155High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read202111,101,010Sensing circuits for charge trap transistors202111,037,873Hermetic barrier for semiconductor device202111,024,347Multiple sense amplifier and data path-based pseudo dual port SRAM202111,010,133Parallel-prefix adder and method202110,991,428Ternary content addressable memory202110,978,143Multi-port high performance memory202110,955,474Customer-transparent logic redundancy for improved yield202110,950,325Memory built-in self test error correcting code (MBIST ECC) for low voltage memories202110,839,931Zero test time memory using background built-in self-test202010,796,750Sequential read mode static random access memory (SRAM)202010,795,430Activity-aware supply voltage and bias voltage compensation202010,748,635Dynamic power analysis with per-memory instance activity customization202010,705,797Parallel-prefix adder and method202010,566,058Ternary content addressable memory202010,551,436Customer-transparent logic redundancy for improved yield202010,489,455Scoped search engine201910,446,233Sense-line muxing scheme201910,438,678Zero test time memory using background built-in self-test201910,295,592Pre-test power-optimized bin reassignment following selective voltage binning201910,217,507Bending circuit for static random access memory (SRAM) self-timer201910,204,685Ternary content addressable memory20199,967,825Environmentally aware mobile computing devices20189,916,896'Ternary content addressable memory (TCAM) for multi bit miss detect circuit'20189,893,765'Transmission system having duplicate transmission systems for individualized precharge and output timing'20189,886,998'Self pre-charging memory circuits'20189,870,163'Double bandwidth algorithmic memory array'20189,865,486'Timing/power risk optimized selective voltage binning using non-linear voltage slope'20189,859,873'Minimization of bias temperature instability (BTI) degradation in circuits'20189,859,006'Algorithmic N search/M write ternary content addressable memory (TCAM)'20189,791,507'Customer-transparent logic redundancy for improved yield'20179,759,767'Pre-test power-optimized bin reassignment following selective voltage binning'20179,760,673'Application specific integrated circuit (ASIC) test screens and selection of such screens'20179,704,575'Content-addressable memory having multiple reference matchlines to reduce latency'20179,601,200'TCAM structures with reduced power supply noise'20179,583,192'Matchline precharge architecture for self-reference matchline sensing'20179,542,981'Self-timed, single-ended sense amplifier'20179,530,500'Converting an XY TCAM to a value TCAM'20169,501,607'Composite views for IP blocks in ASIC designs'20169,472,269'Stress balancing of circuits'20169,384,835'Content addressable memory early-predict late-correct single ended sensing'20169,286,980'Converting an XY TCAM to a value TCAM'20169,281,023'Single ended sensing circuits for signal lines'20169,274,171'Customer-transparent logic redundancy for improved yield'20169,269,440'High density search engine'20169,251,890'Bias temperature instability state detection and correction'20169,224,091'Learning artificial neural network using ternary content addressable memory (TCAM)'20159,218,880'Partial update in a ternary content addressable memory'20159,177,646'Implementing computational memory from content-addressable memory'20159,172,371'Majority dominant power scheme for repeated structures and structures thereof'20159,171,125'Limiting skew between different device types to meet performance requirements of an integrated circuit'20159,088,277'Leakage reduction in output driver circuits'20159,082,484'Partial update in a ternary content addressable memory'20159,058,903'Methods and circuits for disrupting integrated circuit function'20158,929,116'Two phase search content addressable memory with power-gated main-search'20158,848,414'Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system'20148,839,159'Determining overall optimal yield point for a semiconductor wafer'20148,793,365'Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes'20148,654,594'Vdiff max limiter in SRAMs for improved yield and power'20148,582,351'Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability'20138,525,546'Majority dominant power scheme for repeated structures and structures thereof'20138,521,500'Method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models'20138,437,201'Word-line level shift circuit'20138,363,453'Static random access memory (SRAM) write assist circuit with leakage suppression and level control'20138,302,037'Skewed double differential pair circuit for offset cancellation'20128,233,302'Content addressable memory with concurrent read and search/compare operations at the same memory cell'20128,233,337'SRAM delay circuit that tracks bitcell characteristics'20128,228,713'SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same'20128,218,378'Word-line level shift circuit'20128,214,699'Circuit structure and method for digital integrated circuit performance screening'20128,130,525'Method and apparatus for configuring a content-addressable memory (CAM) design as binary CAM or ternary CAM'20128,117,567'Structure for implementing memory array device with built in computation capability'20128,077,534'Adaptive noise suppression using a noise look-up table'20118,016,482'Method and systems of powering on integrated circuit'20117,986,571'Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines'20117,940,581'Method for low power sensing in a multi-port SRAM using pre-discharged bit lines'20117,924,588'Content addressable memory with concurrent two-dimensional search capability in both row and column directions'20117,898,286'Critical path redundant logic for mitigation of hardware across chip variation'20117,859,878'Design structure for implementing matrix-based search capability in content addressable memory devices'20107,859,921'Apparatus and method for low power sensing in a multi-port SRAM using pre-discharged bit lines'20107,848,128'Apparatus and method for implementing matrix-based search capability in content addressable memory devices'20107,830,727'Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines'20107,826,288'Device threshold calibration through state dependent burn-in'20107,823,107'Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design'20107,770,139'Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20107,751,218'Self-referenced match-line sense amplifier for content addressable memories'20107,743,270'Assigning clock arrival time for noise reduction'20107,735,046'E-fuse and method'20107,724,559'Self-referenced match-line sense amplifier for content addressable memories'20107,716,007'Design structures of powering on integrated circuit'20107,705,626'Design structure to eliminate step response power supply perturbation'20107,688,610'Low power match-line sensing circuit'20107,688,611'CAM asynchronous search-line switching'20107,646,648'Apparatus and method for implementing memory array device with built in computational capability'20107,643,591'Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design'20107,515,449'CAM asynchronous search-line switching'20097,511,528'Device and method to eliminate step response power supply perturbation'20097,511,980'Low power match-line sensing circuit'20097,483,806'Design structures, method and systems of powering on integrated circuit'20097,429,877'Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20087,403,039'Flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20087,362,138'Flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20087,227,766'Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories'20077,218,135'Method and apparatus for reducing noise in a dynamic manner'20077,006,368'Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2010Based in South Burlington, VT, US· patent location history
2007–2021Patents assigned to IBM (71)· patent assignee history
2007–2021Based in Williston, VT, US· patent location history
2011–2021Patents assigned to ARSOVSKI IGOR (18)· patent assignee history
2012–2014Patents assigned to PILO HAROLD (7)· patent assignee history
2012Based in Essex Junction, VT, US· patent location history
2015–2021Patents assigned to GLOBALFOUNDRIES INC (28)· patent assignee history
2020–2021Patents assigned to MARVELL ASIA PTE LTD (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM712007–2021
GLOBALFOUNDRIES INC282015–2021
ARSOVSKI IGORself182011–2021
MARVELL ASIA PTE LTD82020–2021
PILO HAROLD72012–2014
Locations
LocationPatentsSpan
Williston, VT, US1002007–2021
South Burlington, VT, US42006–2010
Essex Junction, VT, US12012