Inventor
Hsun-Chung Kuang
Inventor
Hsinchu, TW
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10DInorganic electric semiconductor devices7%
H10NElectric solid-state devices not otherwise provided for7%
B24BMachines, devices, or processes for grinding or polishing6%
H10BElectronic memory devices4%
B23KSoldering or unsoldering1%
C25FProcesses for the electrolytic removal of materials from objects1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
PatentTitleYear
11,049,767Semiconductor device and methods of manufacturing thereof202110,879,077Planarization apparatus and planarization method thereof202010,857,651Apparatus of chemical mechanical polishing and operating method thereof202010,790,1893D integrated circuit and methods of forming the same202010,727,077Structure and method to expose memory cells with different sizes202010,665,449Integrate rinse module in hybrid bonding platform202010,529,913Techniques for MRAM MTJ top electrode connection202010,510,563Wafer carrier assembly201910,350,726Chemical mechanical polishing system and method201910,304,903Semiconductor structure201910,181,441Through via structure and manufacturing method thereof201910,163,651Structure and method to expose memory cells with different sizes201810,128,209Wafer bonding process and structure201810,090,1963D integrated circuit and methods of forming the same20189,893,120'Semiconductor structure and method of forming the same'20189,786,628'Air trench in packages incorporating hybrid bonding'20179,502,396'Air trench in packages incorporating hybrid bonding'20169,425,155'Wafer bonding process and structure'20169,257,399'3D integrated circuit and methods of forming the same'20168,810,048'3D IC and 3D CIS structure'20148,334,187'Hard mask for thin film resistor manufacture'20128,080,461'Method of making a thin film resistor'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (4)· patent assignee history
2011–2012Patents assigned to CHAO CHIH-PING (2)· patent assignee history
2011–2012Patents assigned to KUANG HSUN-CHUNG (2)· patent assignee history
2011–2012Patents assigned to LIU MING CHYI (2)· patent assignee history
2011–2012Based in Yangmei Taoyuan, TW· patent location history
2014–2021Based in Hsinchu, TW· patent location history
2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (18)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 18 | 2016–2021 |
| TAIWAN SEMICONDUCTOR MFG | 4 | 2011–2016 |
| CHAO CHIH-PING | 2 | 2011–2012 |
| KUANG HSUN-CHUNGself | 2 | 2011–2012 |
| LIU MING CHYI | 2 | 2011–2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 20 | 2014–2021 |
| Yangmei Taoyuan, TW | 2 | 2011–2012 |