Inventor

Harshvardhan Sharangpani

Inventor

Santa Clara, CA, US

Overview

1994–2021

Patent span

Physics

Primary field (CPC G)

Patents· 42 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing87%

H03MCoding4%

G01SRadio direction-finding2%

G05BControl or regulating systems in general2%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

11,068,444Using a distributed prime data sieve for efficient lossless reduction, search, and retrieval of data2021 10,108,633Using a distributed prime data sieve for efficient lossless reduction, search, and retrieval of data2018 9,594,765'Performing keyword-based search and retrieval on data that has been losslessly reduced using a prime data sieve'2017 9,582,514'Performing multidimensional search and content-associative retrieval on data that has been losslessly reduced using a prime data sieve'2017 9,292,584'Efficient data communication based on lossless reduction of data by deriving data from prime data elements resident in a content-associative sieve'2016 9,286,313'Efficient lossless reduction of data by deriving data from prime data elements resident in a content-associative sieve'2016 7,464,254'Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data'2008 7,451,143'Programmable rule processing apparatus for conducting high speed contextual searches and characterizations of patterns in data'2008 7,119,577'Method and apparatus for efficient implementation and evaluation of state machines and programmable finite state automata'2006 6,629,232'Copied register files for data processors having many execution units'2003 6,625,693'Fast exception processing'2003 6,611,910'Method for processing branch operations'2003 6,591,359'Speculative renaming of data-processor registers'2003 6,553,488'Method and apparatus for branch prediction using first and second level branch prediction tables'2003 6,401,195'Method and apparatus for replacing data in an operand latch of a pipeline stage in a processor during a stall'2002 6,378,063'Method and apparatus for efficiently routing dependent instructions to clustered execution units'2002 6,272,520'Method for detecting thread switch events'2001 6,240,510'System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions'2001 6,237,077'Instruction template for efficient processing clustered branch instructions'2001 6,233,690'Mechanism for saving power on long latency stalls'2001 6,178,498'Storing predicted branch target address in different storage according to importance hint in branch prediction instruction'2001 6,154,760'Instruction to normalize redundantly encoded floating point numbers'2000 6,105,047'Method and apparatus for trading performance for precision when processing denormal numbers in a computer system'2000 6,065,115'Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction'2000 6,058,410'Method and apparatus for selecting a rounding mode for a numeric operation'2000 5,978,737'Method and apparatus for hazard detection and distraction avoidance for a vehicle'1999 5,922,065'Processor utilizing a template field for encoding instruction sequences in a wide-word format'1999 5,886,915'Method and apparatus for trading performance for precision when processing denormal numbers in a computer system'1999 5,860,017'Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction'1999 5,848,284'Method of transferring data between moderately coupled integer and floating point units'1998 5,832,260'Processor microarchitecture for efficient processing of instructions in a program including a conditional program flow control instruction'1998 5,805,486'Moderately coupled floating point and integer units'1998 5,768,169'Method and apparatus for improved processing of numeric applications in the presence of subnormal numbers in a computer system'1998 5,764,959'Adaptive 128-bit floating point load and store instructions for quad-precision compatibility'1998 5,740,093'128-bit register file and 128-bit floating point load and store for quadruple precision compatibility'1998 5,729,724'Adaptive 128-bit floating point load and store operations for quadruple precision compatibility'1998 5,699,537'Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions'1997 5,590,359'Method and apparatus for generating a status word in a pipelined processor'1996 5,559,977'Method and apparatus for executing floating point (FP) instruction pairs in a pipelined processor by stalling the following FP instructions in an execution stage'1996 5,522,051'Method and apparatus for stack manipulation in a pipelined processor'1996 5,367,650'Method and apparauts for parallel exchange operation in a pipelined processor'1994 5,357,455'Floating point remainder generator for a math processor'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2003Patents assigned to INTEL CORP (29)· patent assignee history

1994–2008Based in Santa Clara, CA, US· patent location history

2001–2003Patents assigned to IDEA CORP (3)· patent assignee history

2006Patents assigned to CISCO SYSTEMS INC (1)· patent assignee history

2008Patents assigned to CISCO TECH INC (2)· patent assignee history

2016–2021Patents assigned to ASCAVA INC (6)· patent assignee history

2016–2021Based in Los Altos Hills, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	29	1994–2003
ASCAVA INC	6	2016–2021
IDEA CORP	3	2001–2003
CISCO TECH INC	2	2008
CISCO SYSTEMS INC	1	2006

Locations

Location	Patents	Span
Santa Clara, California, US	36	1994–2008
Los Altos Hills, California, US	6	2016–2021