Inventor
Chang-Ming Wu
Inventor
New Taipei, TW
Overview
Patents· 82 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices25%
H10BElectronic memory devices24%
H10DInorganic electric semiconductor devices23%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
B81BMicrostructural devices or systems, e.g. micromechanical devices4%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems4%
H01JElectric discharge tubes or discharge lamps1%
C23CCoating metallic material1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
10,870,574Method and apparatus for reducing in-process and in-use stiction for MEMS devices202010,872,895Method of manufacturing capacitor structure202010,868,024Method of forming embedded nonvolatile memory202010,811,504Semiconductor structure for flash memory cells and method of making same202010,784,091Process and related device for removing by-product on semiconductor processing chamber sidewalls202010,766,763Sidewall stopper for MEMS device202010,665,600Memory devices and method of fabricating same202010,562,763Fence structure to prevent stiction in a MEMS motion sensor202010,522,429Method of manufacturing semiconductor device201910,516,026Split gate memory device and method of fabricating the same201910,509,312Approach for ultra thin-film transfer and handling201910,510,763Embedded nonvolatile memory and forming method thereof201910,453,932Semiconductor structure for flash memory cells and method of making same201910,297,604Split gate memory devices and methods of manufacturing201910,294,098Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer201910,273,143Method and apparatus for reducing in-process and in-use stiction for MEMS devices201910,276,584Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates201910,163,692Structure and formation method of interconnection structure of semiconductor device structure201810,147,794Split gate memory device and method of fabricating the same201810,048,220Biosensor field effect transistor having specific well structure and method of forming the same201810,037,893Method and apparatus for etching wafer with etching gas201810,029,910Formation method of MEMS device structure with cavities20189,978,759Memory devices and method of forming same20189,978,603Memory devices and method of fabricating same20189,935,119Dual control gate spacer structure for embedded flash memory20189,917,165'Memory cell structure for improving erase speed'20189,878,899'Method and apparatus for reducing in-process and in-use stiction for MEMS devices'20189,865,610'Si recess method in HKMG replacement gate technology'20189,799,665'Method for forming semiconductor device structure'20179,786,674'Discrete storage element formation for thin-film storage device'20179,748,255'Split gate memory devices and methods of manufacturing'20179,741,868'Self-aligned split gate flash memory'20179,741,728'Method for forming a split-gate flash memory cell device with a low power logic device'20179,728,545'Method for preventing floating gate variation'20179,716,097'Techniques to avoid or limit implant punch through in split gate flash memory devices'20179,711,508'Capacitor structure and method of manufacturing the same'20179,691,883'Asymmetric formation approach for a floating gate of a split gate flash memory structure'20179,679,979'Semiconductor structure for flash memory cells and method of making same'20179,673,204'Semiconductor device structure and method for forming the same'20179,673,205'Embedded nonvolatile memory and forming method thereof'20179,660,188'Phase change memory structure to reduce leakage from the heating element to the surrounding material'20179,653,471'Pattern layout to prevent split gate flash memory cell failure'20179,646,978'Self-aligned flash memory device with word line having reduced height at outer edge opposite to gate stack'20179,620,372'HK embodied flash memory and methods of forming the same'20179,614,048'Split gate flash memory structure and method of making the split gate flash memory structure'20179,589,976'Structure and method to reduce polysilicon loss from flash memory devices during replacement gate (RPG) process in integrated circuits'20179,583,591'Si recess method in HKMG replacement gate technology'20179,570,457'Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates'20179,567,207'Recess with tapered sidewalls for hermetic seal in MEMS devices'20179,570,454'Structure with emedded EFS3 and FinFET device'20179,559,177'Memory devices and method of fabricating same'20179,553,154'Memory devices and method of fabricating same'20179,543,511'RRAM device'20179,536,969'Self-aligned split gate flash memory'20179,536,888'Method to prevent oxide damage and residue contamination for memory device'20179,517,927'MEMS structure having rounded edge stopper and method of fabricating the same'20169,502,514'Memory devices and method of forming same'20169,502,515'Split gate flash memory structure with a damage free select gate and a method of making the split gate flash memory structure'20169,496,276'CMP fabrication solution for split gate memory embedded in HK-MG process'20169,484,351'Split gate memory device and method of fabricating the same'20169,484,352'Method for forming a split-gate flash memory cell device with a low power logic device'20169,472,645'Dual control gate spacer structure for embedded flash memory'20169,450,057'Split gate cells for embedded flash memory'20169,425,044'Composite spacer for silicon nanocrystal memory storage'20169,397,228'Semiconductor device structure and method for forming the same'20169,391,151'Split gate memory device for improved erase speed'20169,391,085'Self-aligned split gate flash memory having liner-separated spacers above the memory gate'20169,356,142'Pattern layout to prevent split gate flash memory cell failure'20169,287,279'Silicon nitride (SiN) encapsulating layer for silicon nanocrystal memory storage'20169,269,829'Split gate flash memory structure with a damage free select gate and a method of making the split gate flash memory structure'20169,257,571'Memory gate first approach to forming a split gate flash memory cell device'20169,159,842'Embedded nonvolatile memory'20159,136,393'HK embodied flash memory and methods of forming the same'20159,082,651'Memory devices and method of forming same'20159,076,681'Memory devices and method of fabricating same'20158,999,833'Method and apparatus for controlling gate dimensions of memory devices'20158,758,984'Method of forming gate conductor structures'20148,420,545'Plasma etching method and plasma etching apparatus for preparing high-aspect-ratio structures'20138,288,261'Method for preparing contact plug structure'20128,178,440'Method for forming a recess array device structure in a semiconductor substrate'20127,335,137'Drive system for magnetic resistance exercisers'20087,303,960'Method for fabricating flash memory device'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2014Patents assigned to NANYA TECHNOLOGY CORP (5)· patent assignee history
2007–2008Based in Taipei, TW· patent location history
2008–2013Patents assigned to WU CHANG MING (4)· patent assignee history
2012–2013Patents assigned to CHEN YI NAN (2)· patent assignee history
2012–2020Based in New Taipei, TW· patent location history
2012Based in Zhonghe, TW· patent location history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (72)· patent assignee history
2015Patents assigned to TAIWAN SEMICONDUCTOR MFG (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 72 | 2015–2020 |
| NANYA TECHNOLOGY CORP | 5 | 2007–2014 |
| TAIWAN SEMICONDUCTOR MFG | 4 | 2015 |
| WU CHANG MINGself | 4 | 2008–2013 |
| CHEN YI NAN | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| New Taipei, TW | 79 | 2012–2020 |
| Taipei, TW | 2 | 2007–2008 |
| Zhonghe, TW | 1 | 2012 |