Inventor
Brian Johnson
Inventor
Boise, ID, US
Overview
Patents· 172 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores25%
G06FElectric digital data processing13%
H03KPulse technique13%
H04LTransmission of digital information, e.g. telegraphic communication5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
Y10TTechnical subjects covered by former us classification2%
H04NPictorial communication, e.g. television2%
LOC182%
B21DWorking or processing of sheet metal or metal tubes, rods or profiles without essentially removing material1%
B65DContainers for storage or transport of articles or materials, e.g. bags, barrels, bottles, boxes, cans, cartons, crates, drums, jars, tanks, hoppers, forwarding containers1%
PatentTitleYear
10,794,080Rapidly deployable modular shelter system202010,757,451User centric service and content curation through in-flight entertainment system202010,732,582Technologies for managing sensor malfunctions202010,690,511Technologies for managing sensor anomalies202010,574,252Frequency management for interference reduction of A/D converters powered by switching power converters202010,392,828Rapidly deployable modular shelter system2019D0849832Point of sale terminal201910,218,374Frequency management for interference reduction of A/D converters powered by switching power converters201910,190,894Technologies for controlling degradation of sensing circuits201910,162,496Presentation of metadata and enhanced entertainment media content201810,163,320Technologies for determining a threat assessment based on fear responses201810,154,011Secure data sharing with publicly accessible computing nodes201810,152,336Technologies for managing sensor conflicts20189,983,565Technologies for bio-chemically controlling operation of a machine20189,970,822Temperature monitoring device for workflow monitoring system20189,890,896'Tilt mechanism for a display monitor'20189,864,858'Technologies for managing security threats to a computing system utilizing user interactions'20189,547,971'Technologies for determining a threat assessment based on fear responses'20179,484,745'Virtual oscillator control of power electronics inverters'20169,378,364'Technologies for managing security threats to a computing system utilizing user interactions'20169,356,795'Communication terminal, wireless communication network system and content distribution method'20169,288,539'System and method for a user interface to manage the recording, downloading and sharing of content from multiple sources'20169,235,323'Techniques for management and presentation of content'20169,224,438'Multiple data rate memory interface architecture'20159,202,082'Secure data sharing with publicly accessible computing nodes'20159,183,513'Aggregration, standardization and extension of social networking contacts to enhance a television consumer experience'20159,094,014'PLD architecture for flexible placement of IP function blocks'20159,080,326'Extendible height container and shelter'20159,058,106'Apparatus, system and method for context and language specific data entry'20158,892,753'System and method for the determination and assignment of a unique local channel identifier (ULCI) to enable the multi-site and multi-user sharing of content'20148,842,454'Inverter array with localized inverter control'20148,782,333'Data storage system, electronic system, and telecommunications system'20148,776,244'System and method for the generation of a content fingerprint for content identification'2014D0707288'Point of sale terminal'2014D0706864'Point of sale terminal'2014D0706863'Point of sale terminal'20148,732,646'PLD architecture for flexible placement of IP function blocks'20148,593,195'High performance memory interface circuit architecture'2013D0689921'Point of sale display'2013D0689381'Handheld temperature monitoring device'20138,487,651'Multiple data rate memory interface architecture'20138,458,147'Techniques for the association, customization and automation of content from multiple sources on a single display'20138,413,072'Apparatus, system and method for context and language specific data entry'20138,407,649'PLD architecture for flexible placement of IP function blocks'20138,332,777'Apparatus, system and method for context and language specific data entry'20128,305,121'High-performance memory interface circuit architecture'20128,225,033'Data storage system, electronic system, and telecommunications system'20128,201,129'PLD architecture for flexible placement of IP function blocks'20128,164,965'Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency'2012D0654493'Mountable stand'20128,093,453'Corn event 3272 and methods of detection thereof'20128,087,433'Methods and apparatus for forming cable media'20127,994,816'Multiple data rate memory interface architecture'20117,969,215'High-performance memory interface circuit architecture'20117,913,035'Method and apparatus for address FIFO for high bandwidth command/address busses in digital storage system'20117,826,283'Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency'20107,800,405'Passgate structures for use in low-voltage applications'20107,746,959'Method and system for generating reference voltages for signal receivers'20107,698,499'Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system'20107,673,254'Apparatus, system and method for context and language specific data entry'20107,635,799'Corn event 3272 and methods for detection thereof'20097,584,447'PLD architecture for flexible placement of IP function blocks'20097,577,212'Method and system for generating reference voltages for signal receivers'20097,557,608'Passgate structures for use in low-voltage applications'20097,535,275'High-performance memory interface circuit architecture'20097,504,855'Multiple data rate memory interface architecture'20097,457,172'Memory device and method having data path with multiple prefetch I/O configurations'20087,450,447'Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency'20087,436,202'Method and apparatus for calibrating driver impedance'20087,331,617'Cabinet door lock'20087,323,903'Soft core control of dedicated memory interface hardware in a programmable logic device'20087,310,276'Memory device and method having data path with multiple prefetch I/O configurations'20077,287,189'I/O configuration and reconfiguration trigger through testing interface'20077,276,949'Multiphase clock generation'20077,269,094'Memory system and method for strobing data, command and address signals'20077,254,067'Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency'20077,251,194'Memory system and method for strobing data, command and address signals'20077,245,553'Memory system and method for strobing data, command and address signals'20077,234,069'Precise phase shifting using a DLL controlled, multi-stage delay chain'20077,227,395'High-performance memory interface circuit architecture'20077,200,022'Apparatus and method for mounting microelectronic devices on a mirrored board assembly'20077,196,542'Techniques for providing increased flexibility to input/output banks with respect to supply voltages'20077,187,617'Memory system and method for strobing data, command and address signals'20077,176,714'Multiple data rate memory interface architecture'20077,173,340'Daisy chaining of serial I/O interface on stacking devices'20077,160,795'Method and structures for reduced parasitic capacitance in integrated circuit metallizations'20077,161,821'Apparatus and method for mounting microelectronic devices on a mirrored board assembly'20077,159,092'Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same'20077,151,707'Memory device and method having data path with multiple prefetch I/O configurations'20067,149,141'Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency'20067,129,738'Method and apparatus for calibrating driver impedance'20067,126,874'Memory system and method for strobing data, command and address signals'20067,123,051'Soft core control of dedicated memory interface hardware in a programmable logic device'20067,119,574'Passage structures for use in low-voltage applications'20067,085,880'Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system'2006D0525282'Point of sale unit having integral customer and operator interfaces'20067,058,920'Methods for designing PLD architectures for flexible placement of IP function blocks'20067,057,967'Multi-mode synchronous memory device and methods of operating and testing same'20067,058,799'Apparatus and method for clock domain crossing with integrated decode'20067,051,982'Fairing arrangements for aircraft'20067,038,966'Memory device and method having data path with multiple prefetch I/O configurations'20067,031,215'Memory device and method having data path with multiple prefetch I/O configurations'20067,030,674'Multiphase clock generators'20067,027,337'Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency'20067,013,252'Simulated circuit node initializing and monitoring'20067,000,872'Circular parachute'20066,970,014'Routing architecture for a programmable logic device'20056,965,249'Programmable logic device with redundant circuitry'20056,958,236'Control of gene expression in plants'20056,934,199'Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency'20056,930,955'Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM'20056,909,196'Method and structures for reduced parasitic capacitance in integrated circuit metallizations'20056,894,551'Multiphase clock generators'20056,889,357'Timing calibration pattern for SLDRAM'20056,882,579'Memory device and method having data path with multiple prefetch I/O configurations'20056,876,562'Apparatus and method for mounting microelectronic devices on a mirrored board assembly'20056,859,065'Use of dangling partial lines for interfacing in a PLD'20056,857,043'Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter'20056,851,016'System latency levelization for read data'20056,842,398'Multi-mode synchronous memory device and methods of operating and testing same'20056,836,166'Method and system for delay control in synchronization circuits'20046,826,741'Flexible I/O routing resources'20046,807,613'Synchronized write data on a high speed memory bus'20046,807,500'Method and apparatus providing improved data path calibration for memory devices'20046,801,989'Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same'20046,762,974'Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM'20046,751,717'Method and apparatus for clock synchronization between a system clock and a burst data clock'20046,732,223'Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system'20046,697,926'Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device'20046,697,297'Apparatus for setting write latency'20046,693,836'Memory device and method having data path with multiple prefetch I/O configurations'20046,690,609'Memory device and method having data path with multiple prefetch I/O configurations'20046,687,185'Method and apparatus for setting and compensating read latency in a high speed DRAM'20046,683,814'Memory device and method having data path with multiple prefetch I/O configurations'20046,678,205'Multi-mode synchronous memory device and method of operating and testing same'20046,674,378'Predictive timing calibration for memory devices'20046,665,223'Memory device and method having data path with multiple prefetch I/O configurations'20036,661,253'Passgate structures for use in low-voltage applications'20036,658,523'System latency levelization for read data'20036,653,862'Use of dangling partial lines for interfacing in a PLD'20036,630,842'Routing architecture for a programmable logic device'20036,605,962'PLD architecture for flexible placement of IP function blocks'20036,605,970'Method and apparatus for crossing from an unstable to a stable clock domain in a memory device'20036,606,041'Predictive timing calibration for memory devices'20036,587,804'Method and apparatus providing improved data path calibration for memory devices'20036,522,172'High speed latch/register'20036,515,914'Memory device and method having data path with multiple prefetch I/O configurations'20036,506,385'Live vaccines and methods of treatment therewith'20036,486,291'Coated porous materials'20026,480,031'High speed latch/register'20026,462,577'Configurable memory structures in a programmable logic device'20026,445,643'Method and apparatus for setting write latency'20026,438,023'Double-edged clocked storage device and method'20026,434,081'Calibration technique for memory devices'20026,414,903'Method and apparatus for crossing clock domain boundaries'20026,411,124'Programmable logic device logic modules with shift register capabilities'20026,401,510'Method for stamping a part from a multi-layered strip'20026,356,110'Multifunction memory array in a programmable logic device'20026,333,893'Method and apparatus for crossing clock domain boundaries'20016,272,070'Method and apparatus for setting write latency'20016,058,444'Self-terminating electrical socket'20005,989,698'Coated porous materials'19995,957,791'Lacrosse stick head with upper string holes and method for stringing same'19995,941,109'Method and apparatus for the registration of containers'19995,893,286'Apparatus and method for the registered embossing of containers'19995,799,525'Tooling and method for the embossing of a container and the resulting container'19985,761,942'Apparatus and method for the embossing of containers'19985,761,854'Collapsible portable containerized shelter'1998D0348654'Hand held terminal with input keyboard and LCD display touch screen'19944,935,287'Stretchable laminate constructions'19904,761,053'Communications transmission media'19884,723,831'Optical fiber communications cable'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2014Patents assigned to MICRON TECHNOLOGY INC (69)· patent assignee history
2001–2014Based in Boise, ID, US· patent location history
2002–2015Patents assigned to ALTERA CORP (35)· patent assignee history
2002–2015Based in Sunnyvale, CA, US· patent location history
2006–2016Patents assigned to JOHNSON BRIAN D (13)· patent assignee history
2006–2016Patents assigned to JOHNSON BRIAN (11)· patent assignee history
2007–2013Based in Issaquah, WA, US· patent location history
2010–2020Patents assigned to INTEL CORP (22)· patent assignee history
2010–2020Based in Portland, OR, US· patent location history
2013–2019Based in Utica, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 69 | 2000–2014 |
| ALTERA CORP | 35 | 2002–2015 |
| INTEL CORP | 22 | 2010–2020 |
| JOHNSON BRIAN Dself | 13 | 2006–2016 |
| JOHNSON BRIANself | 11 | 2006–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 72 | 2001–2014 |
| Sunnyvale, California, US | 30 | 2002–2015 |
| Portland, OR, US | 22 | 2010–2020 |
| Utica, New York, US | 7 | 2013–2019 |
| Issaquah, Washington, US | 5 | 2007–2013 |