Inventor

Alexander Kalnitsky

Inventor

San Francisco, CA, US

Overview

1989–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 201 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices23%

H01LSemiconductor devices16%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%

G11CStatic stores9%

H10BElectronic memory devices8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

H10NElectric solid-state devices not otherwise provided for2%

G01NInvestigating or analysing materials by determining their chemical or physical properties1%

PatentTitleYear

11,133,226FUSI gated device formation2021 11,121,038Spacer structure and manufacturing method thereof2021 11,069,652Method of manufacturing semiconductor structure2021 11,063,157Trench capacitor profile to decrease substrate warpage2021 11,063,080Implant damage free image sensor and method of the same2021 11,063,038Through silicon via design for stacking integrated circuits2021 11,063,081Device over photodetector pixel sensor2021 11,049,797Method for manufacturing a semiconductor structure comprising a semiconductor device layer formed on a tem, porary substrate having a graded SiGe etch stop layer therebetween2021 11,043,531Semiconductor structure and manufacturing method of the same2021 11,037,982Semiconductor structure integrated with magnetic tunneling junction2021 11,029,714Flipped gate current reference and method of using2021 11,011,619Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices2021 10,964,692Through silicon via design for stacking integrated circuits2021 10,879,200Sidewall spacer to reduce bond pad necking and/or redistribution layer necking2020 10,868,243Co-fired passive integrated circuit devices2020 10,854,501Structure and method for enhancing robustness of ESD device2020 10,790,279High voltage integration for HKMG technology2020 10,781,098Method of manufacturing semiconductor structure2020 10,770,598Memory devices and methods of manufacture thereof2020 10,756,086Method for manufacturing semiconductor and structure and operation of the same2020 10,700,001Forming bonding structures by using template layer as templates2020 10,692,914Implant damage free image sensor and method of the same2020 10,665,510Spacer structure and manufacturing method thereof2020 10,649,476Flipped gate current reference and method of using2020 10,629,592Through silicon via design for stacking integrated circuits2020 10,535,629Method of manufacturing semiconductor structure2020 10,535,752Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices2020 10,522,400Embedded temperature control system for a biosensor2019 10,520,467CMOS compatible BioFET2019 10,510,750High voltage integration for HKMG technology2019 10,510,902Memory devices and methods of manufacture thereof2019 10,510,804Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof2019 10,504,892Semiconductor device2019 10,504,958Semiconductor structure and manufacturing method of the same2019 10,431,737Co-fired passive integrated circuit devices2019 10,319,719Semiconductor device structure and manufacturing method thereof2019 10,319,644Method for manufacturing semiconductor structure2019 10,280,076Semiconductor structure and manufacturing method thereof2019 10,269,960Power MOSFETs manufacturing method2019 10,177,187Implant damage free image sensor and method of the same2019 10,164,074Semiconductor device with gate electrode embedded in substrate2018 10,163,849Method of manufacturing semiconductor structure2018 10,157,778Semiconductor structure and manufacturing method thereof2018 10,134,945Wafer to wafer bonding techniques for III-V wafers and CMOS wafers2018 10,128,293Self-aligned back side deep trench isolation structure2018 10,096,523Spacer structure and manufacturing method thereof2018 10,068,945Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof2018 10,062,838Co-fired passive integrated circuit devices2018 10,050,033High voltage integration for HKMG technology2018 10,043,919Memory devices and methods of manufacture thereof2018 10,043,705Memory device and method of forming thereof2018 10,026,640Structure and method for enhancing robustness of ESD device2018 10,014,293Semiconductor device2018 9,935,147Deep trench isolation structure in image sensor device2018 9,935,047Bonding structures and methods forming the same2018 9,923,013'Sensor device, image sensor array and manufacturing method of sensor device'2018 9,910,009'CMOS compatible BioFET'2018 9,853,148Power MOSFETs and methods for manufacturing the same2017 9,818,788'Vertical transfer gate structure for a back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor using global shutter capture'2017 9,799,625'Semiconductor structure and manufacturing method thereof'2017 9,791,406'CMOS compatible BioFET'2017 9,768,218'Self-aligned back side deep trench isolation structure'2017 9,722,015'Capacitor structure and method for manufacturing the same'2017 9,691,725'Integrated semiconductor device and wafer level method of fabricating the same'2017 9,666,574'Semiconductor device structure and manufacturing method thereof'2017 9,627,275'Hybrid semiconductor structure on a common substrate'2017 9,601,411'Semiconductor structure'2017 9,590,504'Flipped gate current reference and method of using'2017 9,553,087'Semiconductor device'2017 9,520,433'Method of fabricating deep trench isolation structure in image sensor and device thereof'2016 9,515,116'Vertical transfer gate structure for a back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor using global shutter capture'2016 9,459,234'CMOS compatible BioFET'2016 9,437,494'Semiconductor arrangement and formation thereof'2016 9,431,107'Memory devices and methods of manufacture thereof'2016 9,422,151'Semiconductor device and manufacturing method thereof'2016 9,343,542'Method for fabricating enhancement mode transistor'2016 9,293,431'Integrated semiconductor device and wafer level method of fabricating the same'2016 9,236,326'Semiconductor structure and fabricating method thereof'2016 9,209,683'Structure and method for a switched circuit device'2015 9,123,671'Silicon wafer strength enhancement'2015 9,076,577'Resistor arrangement and method of use'2015 8,895,993'Low gate-leakage structure and method for gallium nitride enhancement mode transistor'2014 8,857,260'Motion detection using capacitor having different work function materials'2014 8,723,123'Light detector with Ge film'2014 8,647,971'Method of manufacturing junction barrier schottky diode with dual silicides'2014 8,549,922'Motion detection using capacitor having different work function materials'2013 8,456,410'Backlight control using light sensors with infrared suppression'2013 8,345,488'Flash memory array of floating gate-based non-volatile memory cells'2013 8,325,522'Memory array of floating gate-based non-volatile memory cells'2012 8,320,180'Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general purpose CMOS technology with thick gate oxide'2012 8,315,100'Memory array of floating gate-based non-volatile memory cells'2012 8,309,994'Light sensors with infrared suppression'2012 8,218,370'Memory array of floating gate-based non-volatile memory cells'2012 8,101,511'Method of manufacturing a junction barrier Schottky diode with dual silicides'2012 8,080,461'Method of making a thin film resistor'2011 8,000,139'Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general purpose CMOS technology with thick gate oxide'2011 7,960,766'Light sensors with infrared suppression'2011 7,956,432'Photodiode for multiple wavelength operation'2011 7,944,745'Flash memory array of floating gate-based non-volatile memory cells'2011 7,903,465'Memory array of floating gate-based non-volatile memory cells'2011 7,768,273'Electrostatic discharge protection of a capacitive type fingerprint sensing array'2010 7,759,727'Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology'2010 7,755,117'Light sensors with infrared suppression'2010 7,750,426'Junction barrier Schottky diode with dual silicides'2010 7,700,977'Integrated circuit with a subsurface diode'2010 7,688,627'Flash memory array of floating gate-based non-volatile memory cells'2010 7,542,342'Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide'2009 7,522,753'Electrostatic discharge protection of a capacitive type fingerprint sensing array'2009 7,485,486'Photodiode for multiple wavelength operation'2009 7,026,666'Self-aligned NPN transistor with raised extrinsic base'2006 6,987,871'Electrostatic discharge protection of a capacitive type fingerprint sensing array'2006 6,962,842'Method of removing a sacrificial emitter feature in a BICMOS process with a super self-aligned BJT'2005 6,861,324'Method of forming a super self-aligned hetero-junction bipolar transistor'2005 6,855,585'Integrating multiple thin film resistors'2005 6,773,973'Semiconductor transistor having a polysilicon emitter and methods of making the same'2004 6,767,798'Method of forming self-aligned NPN transistor with raised extrinsic base'2004 6,686,250'Method of forming self-aligned bipolar transistor'2004 6,645,803'Method for modifying the doping level of a silicon layer'2003 6,593,640'Bipolar transistor and methods of forming bipolar transistors'2003 6,593,200'Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation'2003 6,531,783'Method of via formation for multilevel interconnect integrated circuits'2003 6,525,397'Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology'2003 6,492,237'Method of forming an NPN device'2002 6,489,217'Method of forming an integrated circuit on a low loss substrate'2002 6,483,931'Electrostatic discharge protection of a capacitve type fingerprint sensing array'2002 6,479,394'Method of low-selective etching of dissimilar materials having interfaces at non-perpendicular angles to the etch propagation direction'2002 6,475,873'Method of forming laser trimmable thin-film resistors in a fully planarized integrated circuit technology'2002 6,420,217'Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology'2002 6,384,398'CMOS compatible pixel cell that utilizes a gated diode to reset the cell'2002 6,380,054'Schottky diode with reduced size'2002 6,380,571'CMOS compatible pixel cell that utilizes a gated diode to reset the cell'2002 6,368,917'Methods of fabricating floating gate semiconductor device with reduced erase voltage'2002 6,365,463'Method for forming a high-precision analog transistor with a low threshold voltage roll-up and a digital transistor with a high threshold voltage roll-up'2002 6,362,050'Method for forming a non-volatile memory cell that eliminates substrate trenching'2002 6,362,023'Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture'2002 6,358,809'Method of modifying properties of deposited thin film material'2002 6,327,187'EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming'2001 6,303,413'Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates'2001 6,277,724'Method for forming an array of sidewall-contacted antifuses having diffused bit lines'2001 6,271,560'Single-poly EPROM cell with CMOS compatible programming voltages'2001 6,262,460'Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor'2001 6,249,010'Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture'2001 6,236,082'Floating gate semiconductor device with reduced erase voltage'2001 6,229,739'Sense amplifier having a bias circuit with a reduced size'2001 6,218,688'Schottky diode with reduced size'2001 6,218,866'Semiconductor device for prevention of a floating gate condition on an input node of a MOS logic circuit and a method for its manufacture'2001 6,208,557'EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming'2001 6,190,968'Method for forming EPROM and flash memory cells with source-side injection'2001 6,188,056'Solid state optical imaging pixel with resistive load'2001 6,184,557'I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection'2001 6,184,552'Non-volatile memory cell with non-trenched substrate'2001 6,180,994'Array of sidewall-contacted antifuses having diffused bit lines'2001 6,177,315'Method of fabricating a high density EEPROM array'2001 6,169,310'Electrostatic discharge protection device'2001 6,166,421'Polysilicon fuse that provides an open current path when programmed without exposing the fuse to the environment'2000 6,157,574'Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data'2000 6,146,962'Method for forming a DRAM cell with a stacked capacitor'2000 6,141,246'Memory device with sense amplifier that sets the voltage drop across the cells of the device'2000 6,137,724'Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages'2000 6,137,721'Memory device having erasable frohmann-bentchkowsky EPROM cells that use a plate-to-floating gate coupled voltage during erasure'2000 6,137,722'Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors'2000 6,137,723'Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure'2000 6,130,840'Memory cell having an erasable Frohmann-Bentchkowsky memory transistor'2000 6,122,204'Sense amplifier having a bias circuit with a reduced size'2000 6,118,691'Memory cell with a Frohmann-Bentchkowsky EPROM memory transistor that reduces the voltage across an unprogrammed memory transistor during a read'2000 6,110,791'Method of making a semiconductor variable capacitor'2000 6,087,211'Method for forming a semiconductor device having non-volatile memory cells, High-voltage transistors, and low-voltage, deep sub-micron transistors'2000 6,081,451'Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages'2000 6,078,211'Substrate biasing circuit that utilizes a gated diode to set the bias on the substrate'2000 6,078,094'Starter current source device with automatic shut-down capability and method for its manufacture'2000 6,055,185'Single-poly EPROM cell with CMOS compatible programming voltages'2000 6,049,202'Reference current generator with gated-diodes'2000 6,031,275'Antifuse with a silicide layer overlying a diffusion region'2000 6,011,859'Solid state fingerprint sensor packaging apparatus and method'2000 6,010,959'Method of improving photoresist adhesion on a dielectric layer'2000 5,998,267'Process to manufacture high density ULSI ROM array'1999 5,982,676'Low voltage generator for bitlines'1999 5,982,669'EPROM and flash memory cells with source-side injection'1999 5,982,608'Semiconductor variable capacitor'1999 5,982,011'Photodiode structure augmented with active area photosensitive regions'1999 5,978,269'Apparatus and method for lowering the potential barrier across the source-to-well junction during the programming of non-volatile memory cells'1999 5,877,541'Contact structure for improving photoresist adhesion on a dielectric layer'1999 5,811,330'Method of fabricating an overvoltage protection device in integrated circuits'1998 5,786,613'Integrated overvoltage protection device having electrodes separated by a gas-filled cavity'1998 5,641,708'Method for fabricating conductive structures in integrated circuits'1997 5,633,178'Method of making volatile memory cell with interface charge traps'1997 5,608,250'Volatile memory cell with interface charge traps'1997 5,589,418'Method of forming a polysilicon buried contact'1996 5,589,708'Radiation hard integrated circuits with implanted silicon in gate oxide layer, field oxide region, and interlevel dielectric layer'1996 5,510,294'Method of forming vias for multilevel metallization'1996 5,470,793'Method of via formation for the multilevel interconnect integrated circuits'1995 5,424,570'Contact structure for improving photoresist adhesion on a dielectric layer'1995 5,418,174'Method of forming radiation hard integrated circuits'1995 5,418,398'Conductive structures in integrated circuits'1995 5,410,174'Contact structure for integrated circuits'1995 5,035,916'Optical waveguide and method for its manufacture'1991 4,968,641'Method for formation of an isolating oxide layer'1990 4,934,774'Optical waveguide and method for its manufacture'1990 4,868,618'Ion implanted semiconductor device'1989 4,859,303'Method and apparatus for removing coating from substrate'1989 4,836,902'Method and apparatus for removing coating from substrate'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2016Patents assigned to KALNITSKY ALEXANDER (18)· patent assignee history

1990–1991Based in Nepean, CA· patent location history

1995–2003Based in Dallas, TX, US· patent location history

1996–2021Based in San Francisco, CA, US· patent location history

1997–2003Based in Grenoble, FR· patent location history

1999–2003Patents assigned to NAT SEMICONDUCTOR CORP (46)· patent assignee history

2001–2006Patents assigned to MAXIM INTEGRATED PRODUCTS (15)· patent assignee history

2001–2006Based in Portland, OR, US· patent location history

2009–2014Patents assigned to INTERSIL INC (21)· patent assignee history

2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (75)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	75	2016–2021
NAT SEMICONDUCTOR CORP	46	1999–2003
INTERSIL INC	21	2009–2014
KALNITSKY ALEXANDERself	18	1990–2016
MAXIM INTEGRATED PRODUCTS	15	2001–2006

Locations

Location	Patents	Span
San Francisco, California, US	161	1996–2021
Portland, OR, US	14	2001–2006
Dallas, Texas, US	11	1995–2003
Grenoble, FR	5	1997–2003
Nepean, CA	3	1990–1991