Nonvolatile semiconductor memory device and producing method thereof

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-208421, filed on Aug. 13, 2008, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to a nonvolatile semiconductor memory device having a multi-layer structure in which cross-point memory cells are laminated and a producing method thereof.

2. Description of the Related Art

Conventionally, a flash memory is well known as an electrically-rewritable nonvolatile memory. In the flash memory, NAND connection or NOR connection of memory cells having floating gate structures is established to form a memory cell array. A ferroelectric memory is also well known as a nonvolatile, high-speed random access memory.

On the other hand, a resistance change type memory in which a variable resistive element is used in the memory cell is proposed as a technique of further achieving a finer design rule of the memory cell. Examples of the variable resistive element include a phase-change memory element in which a resistance value is changed according to a state change between crystalline state and an amorphous state of a chalcogenide compound, an MRAM element in which a resistance change of a tunnel magnetoresistive effect is used, a memory element of a polymer ferroelectric RAM (PFRAM) in which the resistive element is made of a conductive polymer, and an ReRAM element in which the resistance change is generated by electric pulse application (for example, see Japanese Patent Application Laid-Open No. 2006-344349, paragraph [0021]).

In the resistance change type memory, because the memory cell can be formed by a series circuit of a Schottky diode and a resistance change element instead of a transistor, advantageously a three-dimensional structure is formed by ease lamination to achieve the further integration (for example, see Japanese Patent Application Laid-Open No. 2005-522045).

However, even if the resistance change type memory is used, there is a limitation to L/S (Line/Space) of about 40 nm of the memory cell array in a current lithography technique. Therefore, there is a demand for the finer design rule of the memory cell.

A nonvolatile semiconductor memory device according to one aspect of the present invention including: a semiconductor substrate; and a cell array formed on the semiconductor substrate, including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, wherein the cell array includes: a memory cell region where the memory cells are formed; and a peripheral region that is provided around the memory cell region, in the memory cell region, the first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction, in the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line, in the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line, and the contact connecting portion is formed so as to contact with a contact plug extended in a laminating direction.

A nonvolatile semiconductor memory device according to another aspect of the present invention including: a semiconductor substrate; and a cell array formed on the semiconductor substrate, including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, wherein the cell array includes: a memory cell region where the memory cells are formed; and a peripheral region that is provided around the memory cell region, in the memory cell region, the first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction, in the peripheral region, each plurality of continuous first lines alternately have contact connecting portions one end side and the other end side in the first direction of the first line, and the contact connecting portion is formed so as to contact with a contact plug extended in a laminating direction.

A nonvolatile semiconductor memory device producing method according to still another aspect of the present invention including: forming a laminated structure on a semiconductor substrate; and etching the laminated structure to form a cell array, the cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, wherein the method comprises: forming a first mask on the laminated structure, forming a second mask having a predetermined pattern on a layer upper than a layer in which the first mask is formed, slimming the second mask, forming a third mask on a sidewall of the second mask, removing the second mask in a first region, etching the first mask and the laminated structure by means of the third mask in the first region, and etching the first mask and the laminated structure by means of the third mask and the second mask in a second region that is different from the first region.

FIG. 1 is a block diagram illustrating a nonvolatile semiconductor memory device according to a first embodiment of the present invention;

FIG. 2A is a perspective view illustrating a memory cell array 1 (unit cell array MAT 00 to MAT 04 ) of the nonvolatile semiconductor memory device of the first embodiment;

FIG. 2B is a partially enlarged perspective view (perspective view illustrating the unit cell array MAT 01 ) illustrating the memory cell array 1 of FIG. 2A ;

FIG. 3A is a sectional view taken on a line I-I′ of FIG. 2B ;

FIG. 3B illustrates a specific example of an ohmic element NO of FIG. 2B ;

FIG. 4 is a sectional view schematically illustrating an example of a variable resistive element of the first embodiment;

FIG. 5 is a sectional view illustrating a laminated structure of the unit cell array MAT 01 of the first embodiment;

FIG. 6A is a top view illustrating a first metal 27 and a second metal 36 ;

FIG. 6B is a top view illustrating the first metal 27 and the second metal 36 ;

FIG. 6C is a top view illustrating the first metal 27 and the second metal 36 ;

FIG. 7 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the first embodiment;

FIG. 8 is a perspective view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 9 is a perspective view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 10 is a perspective view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 11 is a perspective view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 12 is a perspective view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 13 is a perspective view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 14A is a top view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 14B is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 15 is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 16 is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 17A is a top view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 17B is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 18 is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 19A is a top view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 19B is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 20 is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 21A is a top view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 21B is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 22A is a top view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 22B is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 23A is a top view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 23B is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 24 is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 25A is a top view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 25B is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 26 is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 27A is a top view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 27B is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 28 is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 29 is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 30 is a sectional view illustrating a process for producing the nonvolatile semiconductor memory device of the first embodiment;

FIG. 31 is a top view illustrating a first metal 27 ′ and a second metal 36 ′ of a nonvolatile semiconductor memory device according to a second embodiment of the present invention;

FIG. 32 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the second embodiment;

FIG. 33 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of a third embodiment of the present invention

FIG. 34 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of a fourth embodiment of the present invention;

FIG. 35 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of a fifth embodiment of the present invention;

FIG. 36 is a perspective view illustrating a unit cell array MATa 1 according to a sixth embodiment of the present invention;

FIG. 37 is a sectional view taken on a line II-II′ of FIG. 36 ;

FIG. 38 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the sixth embodiment;

FIG. 39 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of a seventh embodiment of the present invention; and

FIG. 40 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of an eighth embodiment of the present invention.

FIG. 41 is a view illustrating a first metal 27 AA and a second metal 36 AA of an other embodiment of the present invention.

FIG. 42 is a view illustrating a first metal 27 AB and a second metal 36 AB of an other embodiment of the present invention.

Exemplary embodiments of the present invention will be described below with reference to the drawings.

First Embodiment

Schematic Configuration of Nonvolatile Semiconductor Memory Device of First Embodiment

A schematic configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4 . FIG. 1 is a block diagram illustrating a nonvolatile semiconductor memory device (nonvolatile memory) of the first embodiment.

The nonvolatile semiconductor memory device of the first embodiment includes a memory cell array 1 in which memory cells are arranged in a matrix shape, and a later-mentioned ReRAM (variable resistive element) is used in the memory cell. A column control circuit 2 is provided adjacent to the memory cell array 1 in a direction of a bit line BL. The column control circuit 2 controls the bit line BL of the memory cell array 1 , erases data of the memory cell, writes the data in the memory cell, and reads the data from the memory cell. A row control circuit 3 is provided adjacent to the memory cell array 1 in a direction of a word line WL. The row control circuit 3 selects the word line WL of the memory cell array 1 , erases the data of the memory cell, writes the data in the memory cell, and applies a voltage necessary to read the data from the memory cell.

A data input and output buffer 4 is connected to an external host (not illustrated) through an I/O line. The data input and output buffer 4 receives write data, an erase command, an address data, and a command data, and the data input and output buffer 4 supplies read data. The data input and output buffer 4 transmits the received write data to the column control circuit 2 , and the data input and output buffer 4 receives the data read from the column control circuit 2 and supplies the data to the outside. An address supplied from the outside to the data input and output buffer 4 is transmitted to the column control circuit 2 and the row control circuit 3 through an address register 5 . A command supplied from the host to the data input and output buffer 4 is transmitted to a command interface 6 . The command interface 6 receives an external control signal from the host, and the command interface 6 determines whether the data fed into the data input and output buffer 4 is the write data, the command, or the address. When the data is the command, the command interface 6 receives the command and transfers the command as a command signal to a state machine 7 . The state machine 7 manages the whole of, the nonvolatile memory. The state machine 7 receives the command from the host, and performs read, write, and erase of the command and management of data input and output. The external host receives status information managed by the state machine 7 , and the external host can make a determination of operation result. The status information is also utilized in controlling the data write and erase.

The state machine 7 controls a pulse generator 9 . The control enables the pulse generator 9 to supply a pulse at arbitrary timing with an arbitrary voltage. The pulse can be transferred to an arbitrary interconnection that is selected by the column control circuit 2 and the row control circuit 3 .

Peripheral circuit elements except for the memory cell array 1 can be formed on a silicon substrate immediately below the memory array 1 formed in an interconnection layer, and therefore a chip area of the nonvolatile memory can substantially be equalized to an area of the memory cell array 1 .

FIG. 2A is a perspective view of the memory cell array 1 . FIG. 2B is a partially enlarged perspective view of the memory cell array 1 . FIG. 3A is a sectional view of one memory cell taken on a line I-I′ of FIG. 2B .

Referring to FIG. 2A , the memory cell array 1 is divided into four unit cell arrays MAT 01 to MAT 04 . Each of the unit cell arrays MAT 01 to MAT 04 has a part of the memory cell array 1 . The unit cell arrays MAT 01 to MAT 04 are disposed while three-dimensionally laminated as illustrated in FIG. 2A (the unit cell arrays MAT 01 to MAT 04 are disposed from a lower layer to an upper layer). FIG. 2A illustrates the memory cell array 1 by way of example only. The memory cell array 1 may have at least four unit cell arrays. In the memory cell array 1 , the unit cell arrays may be disposed in a two-dimensional direction.

As illustrated in FIG. 2A , the unit cell array MAT 01 includes plural word lines WL 0 ia (in FIG. 2A , i−0 to 2) and plural bit lines BLia. Similarly, as illustrated in FIG. 2A , the unit cell array MAT 02 includes plural word lines WLib and plural bit lines BLib. The unit cell array MAT 03 includes plural word lines WLi and plural bit lines BLic. The unit cell array MAT 04 includes plural word lines WLid and plural bit lines BLid. In FIG. 2A , “i” is set in the range of 0 to 2 by way of example. Alternatively “i” may be set at 3 or more.

The plural word lines WLia are arranged in parallel with one another. The plural bit lines BLia are arranged in parallel with one another while intersecting the plural word lines WLia. A memory cell MC is disposed at each intersecting portion so as to be sandwiched between the interconnections. Desirably the word line WLia and the bit line BLia is made of a heat-resistant, low-resistance material such as W, WSi, NiSi, and CoSi. The plural word lines WLib, WLic, and WLid have the same configuration as the word line WLia. The plural bit lines BLib, the bit line BLic, and the bit line BLid have the same configuration as the bit line BLia.

Referring to FIG. 3A , the memory cell MC includes a circuit of a variable resistive element VR and a non-ohmic element NO are connected in series.

In the variable resistive element VR, a resistance value can be changed by voltage application through an electric current, heat, chemical energy, and the like. Electrodes EL 1 and EL 2 that acts as a barrier metal and a bonding layer are disposed on and beneath the variable resistive element VR. Examples of the electrode material include Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co, Ti, TiN, TaN, LaNiO, Al, PtIrOx, PtRhOx, and Rh/TaAlN. A metal film may be inserted so as to uniform orientation. A buffer layer, a barrier metal layer, and a bonding layer may separately be inserted.

A composite compound whose resistance value is changed by movement of a containing positive ion becoming a transition element (ReRAM) can be used as the variable resistive element VR.

Referring to FIG. 3B , the non-ohmic element NO has (a) a MIM (Metal-Insulator-Metal) structure, (b) a PIN structure (P+ Poly-silicon-Intrinsic-N+ Poly-silicon), and the like. Electrodes EL 2 and EL 3 that acts as the barrier metal layer and the bonding layer may be disposed on and beneath the variable resistive element VR. In the case of the MIM structure, a bipolar operation can be performed. In the case of the PIN structure (diode structure), a unipolar operation can be performed due to characteristics thereof.

FIG. 4 illustrates an example of the variable resistive element. In the variable resistive element VR of FIG. 4 , a recording layer 12 is disposed between electrode layers 11 and 13 . The recording layer 12 is made of a composite compound containing at least two kinds of the positive ion elements. The transition element having a d orbital that is incompletely filled with electrons is used as at least one kind of the positive ion element, and the shortest distance between the adjacent positive ion elements is 0.32 nm or less. Specifically, the composite compound is expressed by a chemical formula AxMyXz (A and M are elements different from each other), and the composite compound is formed by materials having crystal structures such as a spinel structure (AM 2 O 4 ), an ilmenite structure (AMO 3 ), a delafossite structure (AMO 2 ) a LiMoN 2 structure (AMN 2 ), a wolframite structure (AMO 4 ), an olivine structure (A 2 MO 4 ), a hollandite structure (AxMO 2 ), a ramsdellite structure (AxMO 2 ), and a perovskite structure (AMO 3 ).

In the example of FIG. 4 , A is zinc (Zn), M is manganese (Mn), and X is oxygen (O). A small white circle in the recording layer 12 indicates a diffuse ion (Zn), a large white circle indicates a negative ion (O), and small black circle indicates a transition element ion (Mn). An initial state of the recording layer 12 is in a high-resistance state. When a negative voltage is applied onto the side of the electrode layer 13 while the electrode layer 11 is set at a fixed potential, the diffuse ions in the recording layer 12 are partially moved onto the side of the electrode layer 13 , and the diffuse ions in the recording layer 12 is decreased relative to the negative ions. The diffuse ions moved onto the side of the electrode layer 13 receive electrons from the electrode layer 13 , and the diffuse ions are deposited as metal, thereby forming the metal layer 14 . In the recording layer 12 , the negative ions become excessive, which increases a valence number of the transition element ion. Therefore, the recording layer 12 has electron conductivity by carrier injection, and a setting operation is completed. In reproduction, a minute electric current may be passed to an extent in which the resistance change is not generated in the material of the recording layer 12 . In order to reset a program state (low-resistance state) to the initial state (high-resistance state), for example, a large current may sufficiently be passed through the recording layer 12 to perform Joule heating, and thereby promoting an oxidation-reduction reaction of the recording layer 12 . Alternatively, the reset operation may be performed by applying an electric field in an opposite direction to the setting operation.

Specific Configuration of Nonvolatile Semiconductor Memory Device of First Embodiment

A specific configuration of the nonvolatile semiconductor memory device of the first embodiment will be described with reference to FIGS. 5 to 7 . FIG. 5 is a partially sectional view illustrating the nonvolatile semiconductor memory device constituting the unit cell array MAT 01 .

Referring to FIG. 5 , an impurity diffused layer 23 and agate electrode 24 of a transistor constituting the peripheral circuit are formed on a silicon substrate 21 in which a well 22 is formed. A first interlayer insulator 25 is deposited on the impurity diffused layer 23 and the gate electrode 24 . A via 26 that reaches a surface of the silicon substrate 21 is appropriately made in the first interlayer insulator 25 . A first metal 27 constituting the word line WLia of the memory cell array 1 is formed on the first interlayer insulator 25 , and the first metal 27 is made of low-resistance metal such as tungsten (W). A barrier metal 28 is formed on the first metal 27 . The barrier metal may be formed beneath the first metal 27 . The barrier metal may be made of one of or both Ti and TiN. A non-ohmic element 29 such as a diode is formed on the barrier metal 28 . In addition to the above-described configuration, an interconnection layer including one or two layers may be formed on the first interlayer insulator layer 25 .

A first electrode 30 , a variable resistive element 31 , and a second electrode 32 are formed on the non-ohmic element 29 in this order. Therefore, the barrier metal 28 to the second electrode 32 are formed as the memory cell MC. The barrier metal may be inserted beneath the first electrode 30 and on the second electrode 32 , or the barrier metal and the bonding layer may be inserted beneath the second electrode 32 and on the first electrode 30 . A gap between the adjacent memory cells MC is filled with a second interlayer insulator 34 and a third interlayer insulator 35 (however, the second interlayer insulator 34 is not illustrated in FIG. 5 ). A second metal 36 is formed on each memory cell MC of the memory cell array, and the second metal 36 constitutes the bit line BLia that is extended in a direction orthogonal to the word line WLia. Thus, the nonvolatile memory that is of a variable resistive memory is formed. In order to realize the multi-layer structure, the lamination from the barrier metal 28 to the second electrode 32 and the formation of the second and third interlayer insulators 34 and 35 between the memory cells MC may be repeated only as needed.

FIGS. 6A to 6C are top views illustrating the first metal 27 (word line WLia). For the second metal 36 (bit line BLia), a basic pattern is almost the same only except that the direction in which the interconnection is extended is different by 90° from that of the first metal 27 . Therefore, the case of the second metal 36 is described by the numeral in a parenthesis just for reference. FIG. 6A illustrates a memory cell region Ar 1 where the memory cell MC is provided, and FIGS. 6B and 6C illustrate a peripheral region Ar 2 provided around the memory cell region Ar 1 . A contact plug extended in a laminating direction is provided in the peripheral region Ar 2 .

Referring to FIG. 6A , in the memory cell region Ar 1 , the first metal 27 is extended in parallel with a row direction, and the first metal 27 includes linear portions 27 a that are arranged at first intervals (for example, 40 nm or less) in a column direction (direction orthogonal to the row direction) In the memory cell region Ar 1 , the second metal 36 that is extended in the direction orthogonal to the first metal 27 is provided above the first metal 27 , and the memory cell MC is formed in the intersecting portion of the first metal 26 and the second metal 36 .

Referring to FIG. 6B , in the peripheral region Ar 2 , each of the first metals 27 located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the column direction from the predetermined position has a contact connecting portion 27 b on one end side in the row direction thereof.

Referring to FIG. 6C , in the peripheral region Ar 2 , each of the first metals 27 located at (4n−1)-th and 4n-th positions in the column direction from the predetermined position has a contact connecting portion 27 b on the other end side in the row direction thereof. That is, each two of the first metals 27 alternately form the contact connecting portions 27 b in the peripheral region Ar 2 at both ends thereof.

The contact connecting portion 27 b is formed so as to contact the contact plug extended in the laminating direction. The contact connecting portion 27 b is integral with the linear portion 27 a. The contact connecting portion 27 b has a width in the column direction, which is larger than that of the linear portion 27 a.

As illustrated in FIGS. 6B and 6C , in the peripheral region Ar 2 , the first metal 27 includes an island portion 27 c that is adjacent to the contact connecting portion 27 b in the row direction. The island portion 27 c is provided while separated from the linear portion 27 a and the contact connecting portion 27 b. The island portion 27 c is formed so as to contact the contact plug.

In the first embodiment, the first metal 27 , the row direction, and the column direction correspond to the first line, the first direction, and the second direction, respectively.

On the other hand, as illustrated in FIG. 6A , in the memory cell region Ar 1 , the second metal 36 is extended in parallel with the column direction, and the second metal 36 includes linear portions 36 a that are arranged at first intervals (for example, 40 nm or less) in the row direction.

As illustrated in FIG. 6B , in the peripheral region Ar 2 , each of the second metals 36 located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the row direction from the predetermined position has a contact connecting portion 36 b on one end side in the column direction thereof.

As illustrated in FIG. 6C , in the peripheral region Ar 2 , each of the second metals 36 located at (4n−1)-th and 4n-th positions in the row direction from the predetermined position has the contact connecting portion 36 b on the other end side in the column direction thereof. That is, each two of the second metals 36 alternately form the contact connecting portions 36 b in the peripheral region Ar 2 at both ends thereof.

The contact connecting portion 36 b is formed so as to contact the contact plug extended in the laminating direction. The contact connecting portion 36 b is integral with the linear portion 36 a. The contact connecting portion 36 b has a width in the row direction, which is larger than that of the linear portion 36 a.

As illustrated in FIGS. 6B and 6C , in the peripheral region Ar 2 , the second metal 36 includes an island portion 36 c that is adjacent to the contact connecting portion 36 b in the column direction. The island portion 36 c is provided while separated from the linear portion 36 a and the contact connecting portion 36 b. The island portion 36 c is formed so as to contact the contact plug.

In the first embodiment, the second metal 36 , the row direction, and the column direction correspond to the first line, the second direction, and the first direction, respectively.

FIG. 7 is a view schematically illustrating the contact plug of the first embodiment. Referring to FIG. 7 , an upper-layer portion is formed on a silicon substrate 51 while roughly including 11 layers (first layer L 1 to eleventh layer L 11 ).

The unit cell arrays MAT 01 to MAT 04 are formed in the third layer L 3 to the ninth layer L 9 . The word line WLia includes the linear portion 27 a, the contact connecting portion 27 b, and the island portion 27 c. The bit line BLia includes the linear portion 36 a, the contact connecting portion 36 b, and the island portion 36 c.

The word line WLia, the bit line BLia, the word line WLib, the bit line BLib, the word line WLic, the bit line BLic, the word line WLid, and the bit line BLid are formed in a lower portion of each of the third layer L 3 to the tenth layer L 10 , respectively.

As illustrated in FIG. 7 , the nonvolatile semiconductor memory device of the first embodiment includes contact plugs ZW 11 to ZW 14 , ZW 21 to ZW 23 , ZW 31 to ZW 33 , ZW 41 , ZW 42 , ZW 51 , ZW 52 , ZW 61 , ZW 71 , and ZW 81 that electrically connect the word lines WLia to WLid to one another in the laminating direction. The nonvolatile semiconductor memory device of the first embodiment includes contact plugs ZB 1 to ZB 5 that electrically connect the bit lines BL 1 a to BL 1 d to one another in the laminating direction.

Contact plugs CS and V 1 and metal interconnections M 0 and M 1 are formed in the first layer L 1 so as to be extended from the upper surface of the first layer L 1 to the silicon substrate 51 , and the contact plugs CS and V 1 and the metal interconnections M 0 and M 1 constitute a lower-layer interconnection unit. The word lines WL 1 a to WL 1 d and the bit lines BL 1 a to BL 1 d are connected through the lower-layer interconnection unit to peripheral circuits such as a row decoder which are formed in the silicon substrate 51 .

At this point, for example, it is assumed that the description of “X 1 to X 2 →Y 1 to Y 2 ” is given when a contact plug X 1 to a contact plug X 2 are formed in a Y 1 -th layer to a Y 2 -th layer. According to the description, a relationship between the contact plug of the first embodiment and the formed layer thereof can be expressed as follows:

<Relationship between Contact Plug and Formed Layer thereof>

ZW 11 to ZW 14 →L 2 ZW 21 to ZW 23 →L 3 ZW 31 to ZW 33 →L 4 ZW 41 to ZW 42 →L 5 ZW 51 to ZW 5 →L 6 ZW 61 →L 7 ZW 71 →L 8 ZW 81 →L 9 to L 10 ZB 1 →L 2 to L 3 ZB 2 →L 4 to L 5 ZB 3 →L 6 to L 7 ZB 4 →L 8 to L 9 ZB 5 →L 10

For example, it is assumed that the description of “Z( 27 b)-X-M 1 ” is given when the contact connecting portion 27 b of the word line Z is connected to a metal interconnection M 1 through a contact plug X. The island portion 27 c of the word line Z is described as “Z( 27 c)”. According to the description, a connection relationship by the contact plug of the first embodiment can be expressed as follows:

<Connection Relationship by Contact Plug>

WLia( 27 b)-ZW 11 -M 1 WLib( 27 b)-ZW 31 -BLia( 36 c)-ZW 21 -WLia( 27 c)-ZW 12 -M 1 WLic( 27 b)-ZW 51 -BLib( 36 c)-ZW 41 -WLib( 27 c)-ZW 32 -BLia( 36 c)-ZW 22 -WLia( 27 c)-ZW 13 -M 1 WLid( 27 b)-ZW 71 -BLic( 36 c)-ZW 61 -WLic( 27 c)-ZW 52 -BLib( 36 c)-ZW 42 -WLib( 27 c)-ZW 33 -BLia( 36 c)-ZW 23 -WLia( 27 c)-ZW 14 -M 1 ZB 5 -BLid( 36 b)-ZB 4 -BLic( 36 b)-ZB 3 -BLib( 36 b)-ZB 2 -BLia( 36 b)-ZB 1 -M 1

Process for Producing Nonvolatile Semiconductor Memory Device of First Embodiment

A process for producing the nonvolatile semiconductor memory device of the first embodiment will be described below. The following producing process describes a process of forming the unit cell array MAT 01 . The unit cell arrays MAT 02 to MAT 04 are produced through the same forming process as the unit cell array MAT 01 .

An FEOL (Front End Of Line) process is performed to form the transistors constituting the necessary peripheral circuits on the silicon substrate 21 , and the first interlayer insulator 25 (see FIG. 5 ) is deposited on the transistors.

Then the upper-layer portion from the first metal 27 is formed.

FIGS. 8 to 13 are perspective views illustrating a process for producing the upper-layer portion in the process order. The process for producing the upper-layer portion will be described with reference to FIGS. 8 to 13 .

As described above, when the first interlayer insulator 25 is formed, a layer 27 A constituting the first metal 27 of the memory cell array 1 is deposited on the first interlayer insulator 25 , a layer 28 A constituting the barrier metal 28 is formed, a layer 29 A constituting the non-ohmic element 29 is deposited, a layer 30 A constituting the first electrode 30 is deposited, a layer 31 A constituting the variable resistive element 31 is deposited, and a layer 32 A constituting the second electrode 32 is deposited. Therefore, the laminated structure of the upper-layer portion of FIG. 8 is formed.

Then, a hard mask (not illustrated) of a TEOS film is formed in the upper surface of the laminated structure, and first anisotropic etching is performed with the hard mask to form a trench T 1 along the word line WL as illustrated in FIG. 9 , thereby separating the laminated body.

Then the second interlayer insulator 34 is embedded in the trench T 1 . A material having a good insulating property, a low capacitance, and a good embedding property is suitable to the second interlayer insulator 34 . Then a planarization process is performed by CMP to perform removal of the excess second interlayer insulator 34 and exposure of the upper electrode 32 . FIG. 10 is a sectional view after the planarization process is performed. A protective film may be formed by oxidizing and nitriding a sidewall of the trench T 1 before the second interlayer insulator 34 is formed. The formation of the protective film can prevent the oxidation.

A layer 36 A made of tungsten that constitutes the second metal 36 is laminated on the planarized portion after CMP. FIG. 11 illustrates the state after the layer 36 A is laminated.

Then, the hard of the TEOS film is formed on the layer 36 A, and second etching is performed with L/S in the direction orthogonal to the first etching. Therefore, as illustrated in FIG. 12 , a trench T 2 is formed along the word line WLia orthogonal to the bit line BLia, and the memory cell MC that is separated into a columnar shape is simultaneously formed in a self-aligned manner at a cross point of the bit line BLia and the word line WLia. Then, as illustrated in FIG. 13 , a cross-point type memory array layer is formed by the embedment and planarization of the third interlayer insulator 35 .

After the films are laminated, the patterning processes are performed twice in the directions orthogonal to each other, whereby the cross-point cell portion is formed in the self-aligned manner with no misalignment. In order to achieve the finer design rule of the memory cell, L/S is a key factor for the finer design rule.

A process for forming the finer laminated structure illustrated in FIGS. 11 and 12 will be described in detail with reference to FIGS. 14A to 30 . In FIGS. 14A to 30 , FIGS. 14A , 17 A, 19 A, 21 A, 22 A, 23 A, 25 A, and 27 A are plan views, and other drawings are sectional view illustrating portions specified by regions A-A′ to S-S′ in the plan views.

Referring to FIGS. 14A and 14B , a hard mask layer (SiO 2 ) 41 , a silicon nitride mask layer (SiN) 42 , a sacrifice layer (SiO 2 ) 43 , an amorphous silicon mask layer (a-Si) 44 , an antireflection coating layer (ARC layer) 45 , and a resist 46 are laminated in this order on the layer 36 A constituting the second metal 36 . The first metal 27 , the layer 28 A, the layer 29 A, the layer 30 A, the layer 31 A, and the layer 32 A are formed below the layer 36 A in the memory cell region Ar 1 . An interlayer insulator layer 36 B is formed below the layer 36 A in the peripheral region Ar 2 .

In the memory cell region Ar 1 , the resist 46 is extended in parallel with the column direction, and the resist 46 includes linear portions 46 a that are formed at second intervals (second interval>first interval) in the row direction.

As illustrated in FIGS. 14A and 14B , in the peripheral region Ar 2 , the resist 46 located at a (2n−1)-th (n is a positive integer) position in the row direction from the predetermined position has a projection 46 b on one end side in the column direction of the linear portion 46 a.

The projection 46 b is projected with a predetermined length in the column direction so as to be extended in the row direction. The projection 46 b is integral with the linear portion 46 a.

As illustrated in FIGS. 14A and 14B , in the peripheral region Ar 2 , the resist 46 located at a 2n-th position in the row direction from the predetermined position has the two projections 46 b on the other end side in the column direction of the linear portion 46 a.

As illustrated in FIGS. 14A and 14B , in the peripheral region Ar 2 , the resist 46 has an island portion 46 c. The island portion 46 c is provided while separated from the linear portion 46 a and the projection 46 b.

In summary, the process illustrated in FIGS. 14A and 14B is a process for forming the hard mask layer 41 (first mask) and the silicon nitride mask layer 42 (first mask) on the laminated structure whose uppermost layer is the layer 36 A.

As illustrated in FIG. 15 , the antireflection coating layer (ARC layer) 45 and the amorphous silicon mask layer 44 are etched with the resist 46 as the mask. The resist 46 is removed after the etching.

As illustrated in FIG. 16 , the antireflection coating layer 45 is removed.

As illustrated in FIGS. 17A and 17B , the sacrifice layer 43 is etched with the amorphous silicon mask layer 44 as the mask. Therefore, the sacrifice layer 43 is formed into the shape similar to that of the resist 46 . That is, as with the resist 46 , the sacrifice layer 43 is formed so as to include the linear portion 43 a, the projection 43 b, and the island portion 43 c.

As illustrated in FIG. 18 , a slimming process is performed to the sacrifice layer 43 . Through the slimming process, the width of the sacrifice layer 43 is decreased.

As illustrated in FIGS. 19A and 19B , the amorphous silicon mask layer 44 is removed.

In summary, the process illustrated in FIGS. 15 to 19B is a process for forming the sacrifice layer 43 (second mask) having the predetermined pattern on the silicon nitride mask layer 42 (first mask).

As illustrated in FIG. 20 , a spacer layer (a-Si) 47 is formed such that the upper surface and side face of the sacrifice layer 43 and the upper surface of the silicon nitride mask layer 42 are covered therewith.

As illustrated in FIGS. 21A and 21B , the spacer layer 47 on the upper surface of the sacrifice layer 43 and the spacer layer 47 on the upper surface of the silicon nitride mask layer 42 are removed. That is, the spacer layer 47 is left only on the sidewall of the sacrifice layer 43 .

In summary, the process illustrated in FIGS. 20 to 21B is a process for forming the spacer layer 47 (third mask) on the sidewall of the sacrifice layer 43 (second mask).

As illustrated in FIGS. 22A and 22B , a resist 48 is formed such that the projection 43 b and island portion 43 c of the sacrifice layer 43 are covered therewith. In other words, the resist 48 is formed such that the linear portion 43 a of the sacrifice layer 43 is removed.

As illustrated in FIGS. 23A and 23B , the linear portion 43 a of the sacrifice layer 43 is etched and removed with the resist 48 as the mask.

As illustrated in FIG. 24 , the resist 48 is removed.

In summary, the process illustrated in FIGS. 22 to 24 is a process for removing the sacrifice layer 43 (second mask) in the first region.

As illustrated in FIGS. 25A and 25B , in the peripheral region Ar 2 , a resist 49 is formed near an end portion in the first direction such that the loop spacer layer 47 is partially exposed.

As illustrated in FIG. 26 , the spacer layer 47 is etched with the resist 49 as the mask such that the loop spacer layer 47 is partially cut.

As illustrated in FIGS. 27A and 27B , the resist 49 is removed.

As illustrated in FIG. 28 , the silicon nitride mask layer 42 is etched with the spacer layer 47 and the sacrifice layer 43 as the mask.

As illustrated in FIG. 29 , the hard mask layer 41 is etched with the spacer layer 47 , the sacrifice layer 43 , and the silicon nitride mask layer 42 as the mask.

As illustrated in FIG. 30 , the memory layer MC is etched with the silicon nitride mask layer 42 and the hard mask layer 41 as the mask. After the process of FIG. 30 , the silicon nitride mask layer 42 and the hard mask layer 41 are removed. The detailed description of the process of FIGS. 11 and 12 is ended. The process of the laminated structure from the first metal 27 to the second electrode 32 of FIGS. 8 to 10 is substantially similar to the process of FIGS. 14A to 30 only except that the process direction is changed by 90°.

In summary, the process illustrated in FIGS. 28 to 30 is a process for etching the hard mask layer 41 (first mask), the amorphous silicon layer 42 , and the laminated structure with the spacer layer 47 (third mask) in the first region. The process illustrated in FIGS. 28 to 30 is also a process for etching the silicon nitride mask layer 42 (first mask), the hard mask layer 41 (first mask), and the laminated structure with the spacer layer 47 (third mask) and the sacrifice layer 43 (second mask) in the predetermined second region different from the first region.

Effect of Nonvolatile Semiconductor Memory Device of First Embodiment

An effect of the nonvolatile semiconductor memory device of the first embodiment will be described below. The nonvolatile semiconductor memory device of the first embodiment is formed in the above-described way, so that the first metal 27 and the second metal 36 can be formed without complicating the shapes of the first metal 27 and second metal 36 so as to establish the contact with the contact plug.

The nonvolatile semiconductor memory device of the first embodiment is formed by the etching while the sacrifice layer 43 and the spacer layer 47 formed on the sidewall of the sacrifice layer 43 are used as the mask. Accordingly, the first metal 27 and the second metal 36 can be processed thinner than a lithography limit value with the finer pitch (for example, the width of 40 nm or less). That is, the occupied area can be reduced in the nonvolatile semiconductor memory device of the first embodiment.

Second Embodiment

Specific Configuration of Nonvolatile Semiconductor Memory Device of Second Embodiment

A specific configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIGS. 31 and 32 . FIG. 31 is a top view illustrating a first metal 27 ′ and a second metal 36 ′ of the nonvolatile semiconductor memory device of the second embodiment. FIG. 32 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the second embodiment. In the second embodiment, the same component as the first embodiment is designated by the same numeral, and the description is omitted.

The nonvolatile semiconductor memory device of the second embodiment includes the first metal 27 similar to that of the first embodiment and a first metal 27 ′ having a shape different from that of the first embodiment. The nonvolatile semiconductor memory device of the second embodiment includes the second metal 36 similar to that of the first embodiment and a second metal 36 ′ having a shape different from that of the first embodiment.

The first metal 27 ′ will be described with reference to FIG. 31 .

Referring to FIG. 31 , in the peripheral region Ar 2 , the first metal 27 ′ includes a contact connecting portion 27 d whose width in the row direction is lower than that of the first embodiment. For example, the width in the row direction of the contact connecting portion 27 d is formed so as to be substantially equal to the width in the column direction of the linear portion 27 a. The contact connecting portion 27 d is formed such that the contact plug contacts the side face of the contact connecting portion 27 d.

Similarly, in the peripheral region Ar 2 , the second metal 36 ′ includes a contact connecting portion 36 d whose width in the column direction is lower than that of the first embodiment. For example, the width in the column direction of the contact connecting portion 36 d is formed so as to be substantially equal to the width in the row direction of the linear portion 36 a. The contact connecting portion 36 d is formed such that the contact plug contacts the side face of the contact connecting portion 36 d.

A configuration of the contact plug of the second embodiment will be described with reference to FIG. 32 . Referring to FIG. 32 , the nonvolatile semiconductor memory device of the second embodiment includes a contact plug different from that of the first embodiment. Referring to FIG. 32 , the upper layer portion is formed on the silicon substrate 51 while roughly including seven layers (first layer La 1 to seventh layer La 7 ). The first layer La 1 has the configuration similar to that of the first layer L 1 of the first embodiment.

As illustrated in FIG. 32 , as with the first embodiment, the word lines WLia and WLic are formed by the first metal 27 . On the other hand, word lines WLib′ and WLid′ are formed by the first metal 27 ′ different from that of the first embodiment. Bit lines BLia′ and BLic′ are formed by the second metal 36 ′ different from that of the first embodiment. On the other hand, as with the first embodiment, the bit lines BLib and BLid are formed by the second metal 36 .

As illustrated in FIG. 32 , the nonvolatile semiconductor memory device of the second embodiment includes contact plugs ZWa 11 , ZWa 21 to ZWa 23 , ZWa 31 , ZWa 32 , and ZWa 41 that electrically connect the word lines WLia to WLid′ to one another in the laminating direction. The nonvolatile semiconductor memory device of the second embodiment includes contact plugs ZBa 1 to ZBa 3 that electrically connect the bit lines BLia′ to BLid to one another in the laminating direction.

The word line WLia, the bit line BLia′, and the word line WLib′ are formed from the lower layer to the upper layer in the third layer La 3 . The bit line BLib is formed in the fourth layer La 4 . The word line WLic, the bit line BLic′, and the word line WLid′ are formed from the lower layer to the upper layer in the fifth layer La 5 . The bit line BLid is formed in the sixth layer La 6 .

According to the expression method similar to that of the first embodiment, a relationship between the contact plug of the second embodiment and the formed layer thereof can be expressed as follows:

<Relationship between Contact Plug and Formed Layer thereof>

ZWa 11 →La 2 ZWa 21 to ZWa 23 →La 2 to La 3 ZWa 31 →La 4 ZWa 32 →La 4 to La 5 ZWa 41 →La 6 ZBa 1 →La 2 to La 3 ZBa 2 →La 4 to La 5 ZBa 3 →La 6

According to the expression method similar to that of the first embodiment, a connection relationship by the contact plug of the second embodiment can be expressed as follows:

<Connection Relationship by Contact Plug>

WLia( 27 b)-ZWa 11 -M 1 WLib′( 27 d)-ZWa 21 -M 1 WLic( 27 b)-ZWa 31 -BLib( 36 c)-ZWa 22 -M 1 ZWa 41 -ZWa 32 -WLid′( 27 d)-ZWa 32 -BLib( 36 c)-ZWa 23 -M 1 ZBa 3 -BLid( 36 b)-ZBa 2 -BLic′( 36 d)-ZBa 2 -BLib( 36 b)-ZBa 1 -BLia′( 36 d)-ZBa 1 -M 1

In the connection relationship by the contact plug, the contact plugs ZWa 21 and ZWa 32 (ZBa 1 and ZBa 2 ) have the structures in which the contact plugs are extended in the laminating direction while contacting the side portion of the contact connecting portion 27 d ( 36 d).

Effect of Nonvolatile Semiconductor Memory Device of Second Embodiment

An effect of the nonvolatile semiconductor memory device of the second embodiment will be described below. As described above, the nonvolatile semiconductor memory device of the second embodiment has the configuration that is substantially similar to that of the first embodiment. Accordingly, the nonvolatile semiconductor memory device of the second embodiment has the effect similar to that of the first embodiment.

Further, unlike the first embodiment, in the nonvolatile semiconductor memory device of the second embodiment, the contact connecting portion 27 d ( 36 d) is formed such that the contact plug contacts the side portion thereof. The contact plugs ZWa 21 and ZWa 32 (ZBa 1 and ZBa 2 ) have the structures in which the contact plugs ZWa 21 and ZWa 32 are extended in the laminating direction while contacting the side portion of the contact connecting portion 27 d ( 36 d). Therefore, the nonvolatile semiconductor memory device of the second embodiment is formed by the seven layers that are fewer than the 11 layers of the first embodiment. Accordingly, the nonvolatile semiconductor memory device of the second embodiment can be produced through the process that is simpler than that of the first embodiment.

Third Embodiment

Specific Configuration of Nonvolatile Semiconductor Memory Device of Third Embodiment

A specific configuration of a nonvolatile semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIG. 33 . FIG. 33 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the third embodiment. In the third embodiment, the same component as the first and second embodiments is designated by the same numeral, and the description is omitted.

The nonvolatile semiconductor memory device of the third embodiment is formed with the number of laminated layers different from those of the first and second embodiments. The nonvolatile semiconductor memory device of the third embodiment includes unit cell arrays MAT 01 ′ to MAT 04 ′ different from those of the first and second embodiments.

Referring to FIG. 33 , the upper layer portion is formed on the silicon substrate 51 while roughly including five layers (first layer Lb 1 to seventh layer Lb 5 ). The first layer Lb 1 has the configuration similar to that of the first layer L 1 of the first embodiment.

The unit cell array MAT 01 ′ includes a word line WLia′ and the bit line BLia′. The word line WLia′ and the bit line BLia′ are formed in the second layer Lb 2 . The word line WLia′ is located above the bit line BLia′. The word line WLia′ is formed by the first metal 27 ′.

Similarly the unit cell array MAT 02 ′ includes a word line WLib′ and the bit line BLib. The word line wLib′ and the bit line BLib are formed in the third layer Lb 3 . The word line WLib′ is located above the bit line BLib.

The unit cell array MAT 03 ′ includes a word line WLic′ and the bit line BLic′. The word line WLic′ and the bit line BLic′ are formed in the third layer Lb 3 . The word line WLic′ is located above the bit line BLic′. The word line WLic′ is formed by the first metal 27 ′.

The unit cell array MAT 04 ′ includes a word line WLid′ and the bit line BLid. The word line WLid′ and the bit line BLid are formed in the fourth layer Lb 4 . The word line WLid′ is located above the bit line BLid.

The nonvolatile semiconductor memory device of the third embodiment includes contact plugs ZWb 11 to ZWb 14 , ZWb 21 to ZWb 23 , and ZWb 31 that electrically connect the word lines WLia′ to WLid′ to one another in the laminating direction. The nonvolatile semiconductor memory device of the third embodiment includes contact plugs ZBb 1 to ZBb 3 that electrically connect the bit lines BLia′ to BLid to one another in the laminating direction.

According to the expression method similar to that of the first embodiment, a relationship between the contact plug of the third embodiment and the formed layer thereof can be expressed as follows:

<Relationship between Contact Plug and Formed Layer thereof>

ZWb 11 to ZWb 14 →Lb 2 ZWb 21 to ZWb 23 →Lb 3 ZWb 31 =Lb 4 ZBb 1 →Lb 2 ZBb 2 →Lb 3 ZBb 3 →Lb 4

According to the expression method similar to that of the first embodiment, a connection relationship by the contact plug of the third embodiment can be expressed as follows:

<Connection Relationship by Contact Plug>

WLia′( 27 d)-ZWb 11 -M 1 WLib′( 27 d)-ZWb 21 -BLib( 36 c)-ZWb 12 -M 1 WLic′( 27 d)-ZWb 22 -BLib( 36 c)-ZWb 13 -M 1 WLid′( 27 d)-ZWb 31 -BLid( 36 c)-ZWb 23 -BLib( 36 c)-ZWb 14 -M 1 ZBb 3 -BLid( 36 b)-ZBb 2 -BLic′( 36 d)-ZBb 2 -BLib( 36 b)-ZBb 1 -BLia′( 36 d)-ZBb 1 -M 1

In the connection relationship by the contact plug, the contact plugs ZWb 11 , ZWb 21 , ZWb 22 , and ZWb 31 (ZBb 1 and ZBb 2 ) have the structures in which the contact plugs are extended in the laminating direction while contacting the side portion of the contact connecting portion 27 d ( 36 d).

Effect of Nonvolatile Semiconductor Memory Device of Third Embodiment

An effect of the nonvolatile semiconductor memory device of the third embodiment will be described below. As described above, the nonvolatile semiconductor memory device of the third embodiment has the configuration that is substantially similar to that of the first embodiment. Accordingly, the nonvolatile semiconductor memory device of the third embodiment has the effect similar to that of the first embodiment.

Further, the nonvolatile semiconductor memory device of the third embodiment is formed by the five layers that are fewer than the seven layers of the second embodiment. Accordingly, the nonvolatile semiconductor memory device of the third embodiment can be produced through the process that is simpler than that of the second embodiment.

Fourth Embodiment

Specific Configuration of Nonvolatile Semiconductor Memory Device of Fourth Embodiment

A specific configuration of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention will be described with reference to FIG. 34 . FIG. 34 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the fourth embodiment. In the fourth embodiment, the same component as the first to third embodiments is designated by the same numeral, and the description is omitted.

As with the third embodiment, the nonvolatile semiconductor memory device of the fourth embodiment includes the unit cell arrays MAT 01 ′ to MAT 04 ′.

Referring to FIG. 34 , the unit cell array MAT 01 ′ includes a word line WLia″ and a bit line BLia″, which are different from those of the first to third embodiments. The unit cell array MAT 02 ′ includes the bit line BLib and a word line WLib″ that is different from those of the first to third embodiments. The unit cell array MAT 03 ′ includes a word line WLic″ and a bit line BLic″, which are different from those of the first to third embodiments. The unit cell array MAT 04 ′ includes the bit line BLid and a word line WLid″ that is different from those of the first to third embodiments.

The word lines WLia″ to WLid″ have a shape in which a through-hole 27 ba is made in the contact connecting portion 27 b. The bit lines BLia″ and BLic″ have a shape in which a through-hole 36 ba is made in the contact connecting portion 36 b.

Unlike the third embodiment, the contact plug ZWb 11 is formed such that the through-hole 27 ba of the word line WLia″ is pierced therethrough. The contact plug ZWb 21 is formed such that the through-hole 27 ba of the word line WLib″ is pierced therethrough. The contact plug ZWb 22 is formed such that the through-hole 27 ba of the word line WLic″ is pierced therethrough. The contact plug ZWb 31 is formed such that the through-hole 27 ba of the word line WLid″ is pierced therethrough.

Unlike the third embodiment, the contact plug ZBb 1 is formed such that the through-hole 36 ba of the bit line BLia″ is pierced therethrough. The contact plug ZBb 2 is formed such that the through-hole 36 ba of the bit line BLic″ is pierced therethrough.

Effect of Nonvolatile Semiconductor Memory Device of Forth Embodiment

An effect of the nonvolatile semiconductor memory device of the fourth embodiment will be described below. As described above, the nonvolatile semiconductor memory device of the fourth embodiment has the configuration that is substantially similar to that of the third embodiment. Accordingly, the nonvolatile semiconductor memory device of the fourth embodiment has the effect similar to that of the third embodiment.

Fifth Embodiment

Specific Configuration of Nonvolatile Semiconductor Memory Device of Fifth Embodiment

A specific configuration of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to FIG. 35 . FIG. 35 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the fifth embodiment. In the fifth embodiment, the same component as the first to fourth embodiments is designated by the same numeral, and the description is omitted.

Referring to FIG. 35 , the upper layer portion is formed on the silicon substrate 51 while roughly including three layers (first layer Lc 1 to third layer Lc 3 ). The first layer Lc 1 has the configuration similar to that of the first layer L 1 of the first embodiment.

As with the third embodiment, the nonvolatile semiconductor memory device of the fifth embodiment includes the unit cell arrays MAT 01 ′ to MAT 04 ′.

As illustrated in FIG. 35 , the unit cell array MAT 01 ′ includes the word line WLia′ and the bit line BLia″. The unit cell array MAT 02 ′ includes the word line WLib′ and the bit line BLib″. The unit cell array MAT 03 ′ includes the word line WLic′ and the bit line BLic″. The unit cell array MAT 04 ′ includes the word line WLid′ and the bit line BLid″. The bit lines BLib″ and BLid″ have a shape in which the through-hole 36 ba is made in the contact connecting portion 36 b. A diameter of the through-hole 36 ba is formed so as to be decreased from the bit lines BLid″ to BLia″ (from the upper layer to the lower layer).

The bit line BLia″, the word line WLia′, the bit line BLib″, the word line WLib′, the bit line BLic″, the word line WLic′, the bit line BLid″, and the word line WLid′ are formed in the second layer Lc 2 from the lower layer to the upper layer.

The nonvolatile semiconductor memory device of the fifth embodiment includes contact plugs ZWc 11 to ZWc 14 that electrically connect the word lines WLia′ to WLid′ to one another in the laminating direction. The nonvolatile semiconductor memory device of the fifth embodiment includes a contact plug ZBc 1 that electrically connects the bit lines BLia″ to BLid″ to one another in the laminating direction.

According to the expression method similar to that of the first embodiment, a relationship between the contact plug of the fifth embodiment and the formed layer thereof can be expressed as follows:

<Relationship between Contact Plug and Formed Layer thereof>

ZWc 11 to ZWc 14 →Lc 2 ZBc 1 →Lc 2

According to the expression method similar to that of the first embodiment, a connection relationship by the contact plug of the fifth embodiment can be expressed as follows:

<Connection Relationship by Contact Plug>

WLia′( 27 d)-ZWc 11 -M 1 WLib′( 27 d)-ZWc 12 -M 1 WLic′( 27 d)-ZWc 13 -M 1 WLid′( 27 d)-ZWc 14 -M 1 ZBc 1 -BLid″( 36 ba)-ZBc 1 -BLic″( 36 ba)-ZBc 1 -BLib″( 36 ba)-ZBc 1 -BLia′ ( 36 ba)-ZBc 1 -M 1

In the connection relationship by the contact plug, the contact plugs ZWc 11 , ZWc 12 , ZWc 13 , and ZWc 14 have the structures in which the contact plugs are extended in the laminating direction while contacting the side portion of the contact connecting portion 27 d. The contact plug ZBc 1 is formed such that the through-hole 36 ba of the bit lines BLia″ to BLid″ is pierced therethrough. That is, the diameter of the contact plug ZBc 1 is formed so as to be decreased in a stepwise manner from the bit lines BLid″ to BLia″ (from the upper layer to the lower layer).

Effect of Nonvolatile Semiconductor Memory Device of Fifth Embodiment

An effect of the nonvolatile semiconductor memory device of the fifth embodiment will be described below. As described above, the nonvolatile semiconductor memory device of the fifth embodiment has the configuration that is substantially similar to that of the fourth embodiment. Accordingly, the nonvolatile semiconductor memory device of the fifth embodiment has the effect similar to that of the fourth embodiment.

Further, the nonvolatile semiconductor memory device of the fifth embodiment is formed by the three layers that are fewer than the five layers of the fourth embodiment. Accordingly, the nonvolatile semiconductor memory device of the fifth embodiment can be produced through the process that is simpler than that of the fourth embodiment.

Sixth Embodiment

Schematic Configuration of Nonvolatile Semiconductor Memory Device of Sixth Embodiment

A nonvolatile semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to FIGS. 36 and 37 . In the sixth embodiment, the same component as the first to fifth embodiments is designated by the same numeral, and the description is omitted.

The nonvolatile semiconductor memory device of the sixth embodiment has a configuration of FIG. 36 . FIG. 36 is a perspective view illustrating a unit cell array MATa of the sixth embodiment. Referring to FIG. 36 , the nonvolatile semiconductor memory device of the sixth embodiment includes a unit cell array MATa that is different from those of the first to fifth embodiments.

As illustrated in FIG. 36 , the unit cell array MATa includes plural bit lines BLL 1 i, plural word lines WLL 1 i, plural bit lines BLL 2 i, plural word lines WLL 2 i, plural bit lines BLL 3 i, plural word lines WLL 3 i, plural bit lines BLL 4 i, plural word lines WLL 4 i, plural bit lines BLL 5 i from the lower layer to the upper layer.

FIG. 37 is a sectional view taken on a line II-II′of FIG. 36 . The word line WLL 1 i is shared by the memory cells MC 0 and MC 1 that are located on and beneath the word line WLL 1 i, the bit line BLL 1 i is shared by the memory cells MC 1 and MC 2 that are located on and beneath the bit line BLL 1 i, and the word line WLL 2 i is shared by the memory cells MC 2 and MC 3 that are located on and beneath the word line WLL 2 i. The word lines WLL 3 i and WLL 4 i and the bit lines BLL 2 i to BLL 4 i are also shared by the memory cells that are located on and beneath the word lines and the bit lines.

The word lines WLL 1 i and WLL 3 i are formed by the first metal 27 . The word lines WLL 2 i and WLL 4 i are formed by the first metal 27 ′. The bit lines BLL 1 i to BLL 4 i are formed by the second metal 36 ′. The bit line BLL 5 i is formed by the second metal 36 .

Specific Configuration of Nonvolatile Semiconductor Memory Device of Sixth Embodiment

A specific configuration of the nonvolatile semiconductor memory device of the sixth embodiment will be described with reference to FIG. 38 . FIG. 38 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the sixth embodiment.

Referring to FIG. 38 , the upper layer portion is formed on the silicon substrate 51 while roughly including six layers (first layer Ld 1 to sixth layer Ld 6 ). The first layer Ld 1 has the configuration similar to that of the first layer L 1 of the first embodiment.

The unit cell array MATa is formed in the second layer Ld 2 to fourth layer Ld 4 .

As illustrated in FIG. 38 , the nonvolatile semiconductor memory device of the sixth embodiment includes contact plugs ZWd 11 , ZWd 12 , ZWd 21 , ZWd 22 , ZWd 31 , and ZWd 41 that electrically connect the word lines WLL 1 i to WLL 4 i to one another in the laminating direction. The nonvolatile semiconductor memory device of the sixth embodiment includes contact plugs ZBd 11 to ZBd 15 , ZBd 21 to ZBd 24 , ZBd 31 , ZBd 32 , and ZBd 41 that electrically connect the bit lines BLL 1 i to BLL 5 i to one another in the laminating direction.

According to the expression method similar to that of the first embodiment, a relationship between the contact plug of the sixth embodiment and the formed layer thereof can be expressed as follows:

<Relationship between Contact Plug and Formed Layer thereof>

ZWd 11 and ZWd 12 →Ld 2 ZWd 21 and ZWd 22 →Ld 3 ZWd 31 →Ld 4 ZWd 41 →Ld 5 ZBd 11 to ZBd 15 →Ld 2 ZBd 21 to ZBd 24 →Ld 3 ZBd 31 to ZBd 32 →Ld 4 ZBd 41 →Ld 5

According to the expression method similar to that of the first embodiment, a connection relationship by the contact plug of the sixth embodiment can be expressed as follows:

<Connection Relationship by Contact Plug>

WLL 3 i( 27 b)-ZWd 21 -WLL 1 i( 27 b)-ZWd 11 -M 1 ZWd 41 -BLL 5 i( 36 c)-ZWd 31 -WLL 4 i( 27 d)-ZWd 31 -WLL 3 i( 27 c)-ZWd 22 -WLL 2 i( 27 d)-ZWd 22 -WLL 1 i( 27 c)-ZWd 12 -M 1 WLL 1 i( 27 c)-ZBd 11 -BLL 1 i( 36 d)-ZBd 11 -M 1 WLL 3 i( 27 c)-ZBd 21 -BLL 2 i( 36 d)-ZBd 21 -WLL 1 i( 27 c)-ZBd 12 -M 1 WLL 3 i( 27 c)-ZBd 22 -BLL 3 i( 36 d)-ZBd 22 -WLL 1 i( 27 c)-ZBd 13 -M 1 BLL 4 i( 36 d)-ZBd 31 -WLL 3 i( 27 c)-ZBd 23 -WLL 1 i( 27 c)-ZBd 14 -M 1 ZBd 41 -BLL 5 i( 36 b)-ZBd 32 -WLL 3 i( 27 c)-ZBd 24 -WLL 1 i( 27 c)-ZBd 15 -M 1

In the connection relationship by the contact plug, the contact plugs ZWd 22 and ZWd 31 have the structures in which the contact plugs are extended in the laminating direction while contacting the side portion of the contact connecting portion 27 d. The contact plugs ZBd 11 , ZBd 21 , ZBd 22 , and ZBd 31 have the structures in which the contact plugs are extended in the laminating direction while contacting the side portion of the contact connecting portion 36 d.

Effect of Nonvolatile Semiconductor Memory Device of Sixth Embodiment

An effect of the nonvolatile semiconductor memory device of the sixth embodiment will be described below. As described above, the nonvolatile semiconductor memory device of the sixth embodiment includes the word lines WLL 1 i to WLL 4 i and the bit lines BLL 1 i to BLL 5 i, which have the configuration substantially similar to that of the first and second embodiments. Accordingly, the nonvolatile semiconductor memory device of the sixth embodiment has the effect similar to that of the first embodiment.

Seventh Embodiment

Specific Configuration of Nonvolatile Semiconductor Memory Device of Seventh Embodiment

A specific configuration of a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to FIG. 39 . FIG. 39 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the seventh embodiment. In the seventh embodiment, the same component as the first to sixth embodiments is designated by the same numeral, and the description is omitted.

As with the sixth embodiment, the nonvolatile semiconductor memory device of the seventh embodiment includes the unit cell array MATa. The nonvolatile semiconductor memory device of the seventh embodiment includes word lines WLL 1 i′ and WLL 3 i′ and a bit line BLL 5 i′, which are different from those of the sixth embodiment.

The word lines WLL 1 i′ and WLL 3 i′ are formed by the first metal 27 ′. The word lines WLL 1 i′ and WLL 3 i′ have the same shape. The word lines WLL 2 i and WLL 4 i have the same shape. The bit line BLL 5 i′ is formed by the second metal 36 ′.

Referring to FIG. 39 , the upper layer portion is formed on the silicon substrate 51 while roughly including three layers (first layer Le 1 to third layer Le 3 ). The first layer Le 1 has the configuration similar to that of the first layer L 1 of the first embodiment.

The unit cell array MATa is formed in the second layer Le 2 .

As illustrated in FIG. 39 , the nonvolatile semiconductor memory device of the seventh embodiment includes contact plugs ZWe 1 and ZWe 2 that electrically connect the word lines WLL 1 i′ to WLL 4 i to one another in the laminating direction. The nonvolatile semiconductor memory device of the seventh embodiment includes contact plugs ZBe 1 to ZBe 5 that electrically connect the bit lines BLL 1 i to BLL 5 i′ to one another in the laminating direction.

According to the expression method similar to that of the first embodiment, a relationship between the contact plug of the seventh embodiment and the formed layer thereof can be expressed as follows:

<Relationship between Contact Plug and Formed Layer thereof>

ZWe 1 and ZWe 2 →Le 2 ZBe 1 to ZBe 5 →Le 2

According to the expression method similar to that of the first embodiment, a connection relationship by the contact plug of the seventh embodiment can be expressed as follows:

<Connection Relationship by Contact Plug>

WLL 3 i′( 27 d)-ZWe 1 -WLL 1 i′( 27 d)-ZWe 1 -M 1 WLL 4 i( 27 d)-ZWe 2 -WLL 4 i( 27 d)-ZWe 2 -M 1 BLL 1 i( 36 d)-ZBe 1 -M 1 BLL 2 i( 36 d)-ZBe 2 -M 1 BLL 3 i( 36 d)-ZBe 3 -M 1 BLL 4 i( 36 d)-ZBe 4 -M 1 BLL 5 i′( 36 d)-ZBe 5 -M 1

In the connection relationship by the contact plug, the contact plugs ZWe 1 and ZWe 2 have the structures in which the contact plugs are extended in the laminating direction while contacting the side portion of the contact connecting portion 27 d. The contact plugs ZBe 1 to ZBe 5 have the structures in which the contact plugs are extended in the laminating direction while contacting the side portion of the contact connecting portion 36 d.

In other words, the word lines WLL 1 i′ and WLL 3 i′ are configured as follows. In the seventh embodiment, the word line WLL 1 i′ constitutes the cell array (first cell array) that is provided at a predetermined lamination position. The word line WLL 3 i′ constitutes the cell array (second cell array) that is provided on the first cell array. The word line WLL 1 i′ included in the first cell array has the same shape as the word line WLL 3 i′ included in the second cell array. In the seventh embodiment, the word line WLL 2 i constitutes the cell array (first cell array) that is provided at a predetermined lamination position. The word line WLL 4 i constitutes the cell array (second cell array) that is provided on the first cell array. The word line WLL 2 i included in the first cell array has the same shape as the word line WLL 4 i included in the second cell array.

Effect of Nonvolatile Semiconductor Memory Device of Seventh Embodiment

An effect of the nonvolatile semiconductor memory device of the seventh embodiment will be described below. As described above, the nonvolatile semiconductor memory device of the seventh embodiment includes the unit cell array MATa having the configuration substantially similar to that of the sixth embodiment. Accordingly, the nonvolatile semiconductor memory device of the seventh embodiment has the effect similar to that of the sixth embodiment.

Further, the nonvolatile semiconductor memory device of the seventh embodiment is formed by the three layers that are fewer than the six layers of the sixth embodiment. Accordingly, the nonvolatile semiconductor memory device of the seventh embodiment can be produced through the process that is simpler than that of the sixth embodiment.

Eighth Embodiment

Specific Configuration of Nonvolatile Semiconductor Memory Device of Eighth Embodiment

A specific configuration of a nonvolatile semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to FIG. 40 . FIG. 40 is a view schematically explaining a contact plug of the nonvolatile semiconductor memory device of the eighth embodiment. In the eighth embodiment, the same component as the first and second embodiments is designated by the same numeral, and the description is omitted.

The nonvolatile semiconductor memory device of the eighth embodiment includes the unit cell array MATa that is similar to that of the sixth embodiment. The nonvolatile semiconductor memory device of the eighth embodiment includes bit lines BLL 2 i′ and BLL 4 i′, which are different from that of the seventh embodiment.

The bit lines BLL 2 i′ and BLL 4 i are formed by the second metal 36 .

Referring to FIG. 40 , the upper layer portion is formed on the silicon substrate 51 while roughly including five layers (first layer Lf 1 to sixth layer Lf 5 ). The first layer Lf 1 has the configuration similar to that of the first layer L 1 of the first embodiment.

The unit cell array MATa is formed in the second to fourth layers Lf 2 to Lf 4 .

As illustrated in FIG. 40 , the nonvolatile semiconductor memory device of the eighth embodiment includes contact plugs ZWf 11 to ZWf 31 that electrically connect the word lines WLL 1 i′ to WLL 4 i to one another in the laminating direction. The nonvolatile semiconductor memory device of the eighth embodiment includes contact plugs ZBf 11 to ZBf 31 that electrically connect the bit lines BLL 1 i to BLL 5 i′ to one another in the laminating direction.

According to the expression method similar to that of the first embodiment, a relationship between the contact plug of the eighth embodiment and the formed layer thereof can be expressed as follows:

<Relationship between Contact Plug and Formed Layer Thereof>

ZWf 11 to ZWf 14 →Lf 2 ZBf 11 and ZBf 12 →Lf 2 ZWf 21 to ZWf 23 →Lf 3 ZBf 21 and ZBf 22 →Lf 3 ZWf 31 →Lf 4 ZBf 31 →Lf 4

According to the expression method similar to that of the first embodiment, a connection relationship by the contact plug of the eighth embodiment can be expressed as follows:

<Connection Relationship by Contact Plug>

BLL 2 i′( 36 c)-ZWf 11 -WLL 1 i′( 27 d)-ZWf 11 -M 1 BLL 4 i′( 36 c)-ZWf 21 -WLL 2 i( 27 d)-ZWf 21 -BLL 2 i′( 36 c)-ZWf 12 -M 1 BLL 4 i′( 36 c)-ZWf 22 -WLL 3 i′( 27 d)-ZWf 22 -BLL 2 i′( 36 c)-ZWf 13 -M 1 ZWf 31 -WLL 4 i( 27 d)-ZWf 31 -BLL 4 i′( 36 c)-ZWf 23 -BLL 2 i′( 36 c)-ZWf 14 -M 1 BLL 4 i′( 36 b)-ZBf 21 -BLL 2 i′( 36 b)-ZBf 1 -M 1 ZBf 31 -BLL 5 i′( 36 d)-ZBf 31 -BLL 4 i′( 36 c)-ZBf 22 -BLL 3 i( 36 d)-ZBf 22 -BLL 2 i′( 36 c)-ZBf 12 -BLL 1 i( 36 d)-ZBf 12 -M 1

In the connection relationship by the contact plug, the contact plugs ZWf 11 , ZWf 21 , and ZWf 31 have the structures in which the contact plugs are extended in the laminating direction while contacting the side portion of the contact connecting portion 27 d. The contact plugs ZBf 11 , ZBf 22 , and ZBf 31 have the structures in which the contact plugs are extended in the laminating direction while contacting the side portion of the contact connecting portion 36 d.

Effect of Nonvolatile Semiconductor Memory Device of Eighth Embodiment

An effect of the nonvolatile semiconductor memory device of the eighth embodiment will be described below. As described above, the nonvolatile semiconductor memory device of the eighth embodiment includes the unit cell array MATa having the configuration substantially similar to that of the sixth embodiment. Accordingly, the nonvolatile semiconductor memory device of the eighth embodiment has the effect similar to that of the sixth embodiment.

Further, the nonvolatile semiconductor memory device of the eighth embodiment is formed by the five layers that are fewer than the six layers of the sixth embodiment. Accordingly, the nonvolatile semiconductor memory device of the eighth embodiment can be produced through the process that is simpler than that of the sixth embodiment.

Other Embodiments

The nonvolatile semiconductor memory devices of the first to eighth embodiments are described above. However, the present invention is not limited to the first to eighth embodiments, but various modifications, additions, and substitutions can be made without departing from the scope of the present invention.

For example, the present invention is not particularly limited to the memory cell structure, but the present invention can be applied to various cross-point type multi-layer memories such as the phase-transition memory element, the MRAM element, PFRAM, and RRAM.

For example, in the first to eighth embodiments, the positions of the word line and bit line may be changed with each other.

For example, instead of interconnection/cell/interconnection/cell illustrated in the sixth and eighth embodiments, an interlayer insulator may be interposed between the cell array layers like interconnection/cell/interconnection/interlayer insulator/interconnection/cell/interconnection.

In the producing method, the memory cell, the word line, and the bit line are formed through the self-aligned process for the laminated body. For example, the word line and the bit line may be formed through a damascene process, and the memory cell may separately be formed on or beneath the word line and the bit line through a pillar forming process.

In the above embodiments, each of two first metal 27 (second first metal 36 ) have alternatively contact connecting portions 27 b ( 36 b) at one end side and the other end side in the row direction (the column direction). However, as shown in FIG. 40 , each of four first metal 27 AA (second first metal 36 AA) having alternatively contact connecting portions 27 AAb ( 36 AAb) at one end side and the other end side in the row direction (the column direction) may be applicable in this invention. Further, as shown in FIG. 41 , each of eight first metal 27 AB (second first metal 36 AB) having alternatively contact connecting portions 27 ABb ( 36 ABb) at one end side and the other end side in the row direction (the column direction) may be applicable in this invention.