Imaging device with pre-charged signal line

The present invention relates to the field of imaging devices, and more specifically to the architecture of the pixel sampling circuitry column signal lines.

Over the past decade, there have been great developments in the field of image sensors, the commercialization of these products have led to increasing amount of consumer and industrial products that have revolutionized the areas of inventory, security, and photography in general. However, there are still problems with the quality of image sensors, and it is the development of solutions for these problems that will allow it to continue to rise in use and application.

One problem that has plagued image sensors is a concept known as “banding”, in particular one type of banding is known as the “first frame effect”. “Banding” occurs during an image capture, and results in a line or “band” of darker pixels appearing in the captured image. This problem can largely be attributed to the parasitic capacitance between the imaging pixel cell and the column signal line, and noise in the power source for the reset voltage, these types of noise are commonly referred to as “reset noise”.

The issue of banding has been dealt with before with some success through the use of a variation on double sampling, in combination with a memory device.

During a normal double sample, which is designed to reduce fixed pattern noise, the pixel is reset, allowed to integrate and then sampled at a sample time. Shortly thereafter, the pixel is reset again and sampled once again so that a second reset voltage for that pixel can be captured. The processing circuitry then compares the captured second reset voltage and the captured sample voltage, in order to determine an actual sample voltage free of the fixed pixel noise.

There is a variation on this technique in the prior art, which allows the imager to reduce “reset noise” as well as the fixed pixel noise. The double sample is performed in the normal manner, however there is a memory device attached to the row, which captures the first reset voltage. This first reset voltage can then be used to determine the noise between the first and second reset voltage, and that information can be used by the imaging process circuitry in order to remove that noise from the actual sample voltage.

In order to accommodate this method of reducing the “reset noise” a memory device must be added to imager. This type of solution focuses on the issue of noise in the voltage supply, but does not address in particular the issue of noise due to parasitic capacitance between the column signal line and the imaging cell.

The “banding” that results from parasitic capacitance, is typically referred to as the “first frame effect”. This type of banding creates a dark line of pixels from the first row that has been reset after the first sample signal has been placed on the column line. This distortion of pixel intensity makes the first frame of the imager unserviceable. In prior art systems this frame has simply been discarded with only the subsequent images being used for the purpose of imaging.

It may be considered that this is an inappropriate solution, as this adds time to the image capture cycle for the imager. Additionally it may be considered that this will lead to problems in some image capture systems, whereby a sequence of frames is being captured, and the first frame is needed in order to accomplish the task for the imager. For example, in a package transportation belt with a stationary mounted imager for decoding bar-codes, the belt speed may prevent a package from being properly scanned. Other examples would be apparent to one skilled in the art that the first frame should not be discarded.

It is to be noted that although a specific imaging architecture has been discussed to illustrate the deficiencies in the prior art, other imaging architectures could contain the same deficiencies. Thus, the problem discussed could occur in other circuits that use a similar technique for pixel readout.

Therefore, there is a need for a method and apparatus for improving image quality from an electronic image by reducing banding resulting from parasitic capacitance between the imaging pixel and the column signal line.

The invention is directed to a method of operating an imaging device having a number of pixels and one or more signal lines, wherein each pixel has a photodetector. The method comprises the steps of applying a precharge voltage to the signal line, resetting the photodetector, integrating the photodetector voltage as light impinges upon it, coupling the photodetector to the signal line, and sampling the integrated voltage coupled to the signal line.

In accordance with another aspect, the invention is directed to a method of operating an imaging device having an array of pixels arranged in rows and columns and a signal line for each column, wherein each pixel has a photodetector. The method comprises the steps of applying a precharge voltage to the signal lines, resetting the photodetectors in a row, integrating the photodetector voltage as light impinges on the reset photodetectors, coupling the integrated photodetectors to the signal lines, and sampling the integrated voltage coupled to each of the signal lines. The above steps are repeated for each of the rows of pixels.

In accordance with a further aspect of the invention, the method includes the steps of resetting the photodetector and sampling the photodetector reset voltage on the signal line.

In accordance with another aspect of the invention, the precharge voltage is applied to the signal line during the integration time of the photodetector.

In accordance with another aspect, the invention is directed to an imaging device comprising a pixel element having a photodetector coupled to a reset switch, said reset switch being adapted to receive a reset signal, a signal line adapted to be selectively coupled to said pixel element and a precharge circuit selectively coupled to said signal line to provide precharge voltage to said signal line.

In accordance with yet another aspect of the invention, the imaging device comprises an array of pixels arranged in rows and columns, column signal lines adapted to be selectively coupled to the rows of pixels at predetermined times, and a precharge circuit adapted to place a voltage on the column signal lines.

In accordance with a specific aspect of this invention, the precharge circuit includes a switch arrangement for connecting the signal line or lines to a precharge voltage supply. The switch arrangement can be a switch for each of the signal lines, a switch for all of the signal lines or a number of switches, each connected to a selected group of signal lines.

In accordance with a further aspect of the invention, the precharge circuit includes a controller for closing the switch or switches when a pixel element is not coupled to the signal line. The controller further includes a detector for sensing the voltage on the signal lines.

In accordance with yet another aspect, the invention is directed to an apparatus for placing a voltage on signal lines of an imaging device, wherein the signal lines are adapted to be selectively coupled to columns of pixels at predetermined times. The apparatus comprises a switch arrangement adapted to connect a voltage supply to the signal lines, and a controller for controlling the switch arrangement to connect the voltage supply means to the signal lines at times other then the predetermined times. The switch arrangement can be a switch for each of the signal lines, a switch for all of the signal lines or a number of switches, each connected to a selected group of signal lines.

In accordance with a specific aspect of the invention, the controller closes the switch when a pixel is not coupled to the signal line and includes a detector for detecting voltage on the signal lines.

Other aspects and advantages of the invention, as well as the structure and operation of various embodiments of the invention, will become apparent to those ordinarily skilled in the art upon review of the following description of the invention in conjunction with the accompanying drawings.

The invention will be described with reference to the accompanying drawings, wherein:

FIG. 1 illustrates a prior art pixel circuit diagram showing the location of the parasitic capacitance that may occur between a CMOS imaging pixel, and the column signal line;

FIG. 2 illustrates a prior art imaging device circuit diagram;

FIG. 3 shows a timing diagram for the imaging device in FIG. 2 ;

FIG. 4 illustrates an embodiment of an imaging device circuit diagram in accordance with the present invention;

FIG. 5 shows a timing diagram for the imaging device in FIG. 4 ;

FIG. 6 illustrates an embodiment of an image device circuit diagram in accordance with the present invention having a separate voltage supply circuit for each column;

FIG. 7 illustrates an embodiment of an image device circuit diagram in accordance with the present invention having a separate voltage supply circuit for preselected blocks of columns; and

FIG. 8 illustrates an embodiment of an image device circuit diagram in accordance with the present invention having a voltage supply circuit with a single switch for all columns.

The present invention provides a method and apparatus for substantially reducing the impact of the first frame effect on electronic imaging devices. For purposes of explanation, specific embodiments are set forth to provide a thorough understanding of the present invention. However, it is to be understood from the present disclosure, that although the present invention is described using CMOS image sensors, most, if not all, aspects of the invention apply to image sensors in general. Moreover, well-known elements, devices, process steps and the like are not set forth in order to provide a clear and simple description of the present invention.

Operation of the various embodiments of the invention will be explained using an NMOS implementation of the circuits. The following abbreviations are used in this disclosure to describe the various operating regions of the FET. A FET is said to be “turned off” when V GS (gate-source voltage)<V T (threshold voltage) for the device and the device is operating in the cut-off region where its channel acts as an open circuit. When a FET is “turned on” (V GS ≧V T ) and V DS (drain-source voltage)≦V GS −V T , the device is operating in the triode region.

Furthermore, logic signals are denoted as being “high” or “low”, this, as is known to one skilled in the art, refers to the first supply voltage of the device, (such as 3.3 V or 5 V) and the second supply voltage of the device, (typically ground). However, the reverse could also be used if the implementation were to use PMOS circuits, or inverters in combination with NMOS circuitry.

Additionally, the terms “active high” and “active low” refer to electronic devices that become turned on, either through the use of a high signal or a low signal, respectively.

The present invention will be described in conjunction with a typical pixel element 135 illustrated in FIG. 1 . However, it will become evident to those skilled in the art that the present invention can be equally applied to numerous other pixel types. Pixel 135 consists of a photodiode element 130 , whose cathode is coupled at node 120 to both the source of a reset transistor 140 and to the gate of a source-follower transistor 145 . The reset transistor 140 has a gate activated by a signal V Reset applied to line 125 , and it is coupled at its drain to a first supply voltage V DD on line 150 . The anode of the photodiode 130 is coupled to a second supply voltage V SS on line 155 . The source-follower transistor 145 is coupled at its drain to the first supply voltage V DD on line 150 , and at its source to the drain of the row access transistor 165 . The row access transistor 165 has a gate activated by a signal V Row — Access on line 105 , and is coupled at its source to the column signal line 100 . This type of pixel 135 has a parasitic capacitance (C ParP ), which is shown as element 115 and will be described below.

Pixel 135 operates as follows. Reset transistor 140 is turned on by the V Reset signal pulse on line 125 at time t 1 . The first voltage supply V DD on line 150 then places a charge, which is approximately equal to the reset voltage V Reset on line 125 subtracting the threshold voltage of the reset transistor 140 (˜V Reset −V T ), on the photodiode 130 cathode coupled to node 120 . This voltage remains floating at the pixel node 120 but is “leaked” slowly by the photodiode 130 to the second voltage supply on line 155 . The rate of leakage depends on the amount of light 160 impinging on the photodiode 130 ; the greater the light intensity that strikes the surface of the photodiode 130 the faster the charge is leaked through to the second voltage supply on line 155 . This charge is allowed to “leak” for a period of time, commonly known as the integration time T INT , essentially the time between the resetting of the pixel 135 and the sampling of the pixel 135 . When the pixel 135 is to be sampled, a V Row — Access signal pulse on line 105 is applied to the gate of transistor 165 , which turns on the row access transistor 165 . The charge on the pixel node 120 is also present on the gate of the source-follower transistor 145 and controls the application of voltage V DD from the first voltage supply on line 150 to the row access transistor 165 . As the row access transistor 165 is now active, a voltage is passed to the column signal line 100 that is approximately equal to the voltage at the pixel node 120 minus the threshold voltages (V T ) of both the source-follower transistor 145 and the row access transistor 165 . At this point the signal can be sent to the processing circuitry coupled to column signal line 100 and the pixel 135 , is considered to have been sampled or read.

In a CMOS imaging device 200 , an imaging array usually consists of several rows and columns of pixel elements 135 , organized in a (m×n) matrix fashion. Typically the number of rows is denoted as m, and the number of columns is denoted as n. Each column line 100 a, 100 b, 100 c . . . is connected to a pixel 135 in each row, typically in a manner as is shown in FIG. 2 , which illustrates, in block diagram form, a 3×3 matrix. Typically an actual imaging device 200 consists of much larger arrays, however the array 200 illustrated is only meant as an example to simplify the explanation of the present invention.

The “banding” or “first frame effect” is illustrated as follows. In a typical video operation mode of the array, the first row 202 a of the array is reset by V Reset — 1 , a pulse on line 225 a followed by the resetting of the second row 202 b, the third row 202 c and so on. Referring to FIG. 3 , the voltage on the pixel nodes for the first row 202 a is raised to the voltage level approximately equivalent to the following formula at time t 1 :

V 120 — R1 (t 1 )=(V Reset — 1 −V T — R1 ).

At this point, the voltage V 100a on the column line 100 a is undefined. For this example it can be assumed that it is at ground, namely V SS . Therefore, the parasitic capacitor 115 will have a charge equivalent to the following formula placed on it:

Q ParP =C ParP *(V Reset — 1 −V T −V SS ).

Later, in turn, the second row of pixels 135 will be reset at time t 4 , the third row at time t 5 , and so on.

With reference to FIGS. 1 and 2 , after the first row was reset and an amount of time, known as the integration time (T INT ), has passed, the V Row — Access signal pulse is applied on line 205 a at time t 2 , and the voltage on the pixel 135 is applied to line 100 a as V 100a (t 2 ) to be sampled by the sampling circuit 295 a. The current sources 270 a, 270 b, 270 c . . . are part of the read-out circuit and may be switched current sources which are accessed during the read-out cycle to pull down the voltage across the diode 130 of each pixel 135 .

V 100a (t 2 )=(V Reset — 1 −2V T −V INT ),

where V INT is the voltage decay or leakage from the diode 130 during the integration period (T INT ).

The pixels 135 of the first row 202 a are then reset to their initial values at time t 3 and sampled again, this is known as double sampling. After this, the column line 100 a is at a voltage V 100a (t 3 ) approximately equal to the following formula:

V 100a (t 3 )˜Y Reset — 1 −2V T .

The effect of this on the other rows that are integrating, for example, as is shown as event 302 in FIG. 3 , is to “pump” the diodes 135 . Since the column 100 a is coupled to the second row 202 b, the diode voltage V 120b will be raised by:

ΔV A ˜(V Reset — 1 −2V T )C ParP /(C ParP +C ParTot )

The voltage V 100a (t 3 ) on line 100 a decays slowly until the read/reset cycle for the next row, however its value generally remains well above V 100a (t 2 ). Therefore a row 202 b, 202 c, . . . that is reset after the columns 100 a, 100 b, 100 c . . . have been raised from their initial value of V SS in this example to about (V SS −2 V T ) will have negligible charge pump effect. This situation is shown in FIG. 3 , as ΔV B during event 303 . This is the source of the “first frame” effect.

It has been determined that holding the column lines 100 a, 100 b, 100 c . . . at a substantially constant voltage when the rows are being reset can significantly reduce the first frame effect. In this way, charge pumping can be reduced. Further, it has been determined that the presence of a voltage level on the column lines 100 a, 100 b, 100 c . . . prior to the pixels 135 being sampled substantially reduces the impact of the column to pixel charge pumping.

The method of reducing banding in accordance with the present invention comprises applying a voltage to the column lines 100 a, 100 b, 100 c . . . in an imaging device 200 while the rows of pixels 135 are being reset and the sampling circuits 295 are not sampling the voltages on the pixel 135 diodes 130 . FIGS. 4 , 6 , 7 and 8 illustrate the imaging devices 400 , 600 , 700 and 800 which include apparatus for accomplishing the method. For clarity and to simplify the description, elements of the imaging devices 400 , 600 , 700 and 800 which are similar to those of the imaging device 200 in FIG. 2 , carry the same reference numbers. This also applies to the timing diagram illustrated in FIG. 5 . In FIG. 4 , the apparatus comprises a voltage supply circuit 475 , which is connected to the column lines 100 a, 100 b, 100 c . . . through switches 480 a, 480 b, 480 c . . . , such that the voltage supply circuit 475 is selectively coupled to the column lines 100 a, 100 b, 100 c . . . .

The voltage supply circuit 475 , also referred to as the precharge circuit, is selected to provide a reasonably constant voltage V PRE to precharge the column line or lines 100 a, 100 b, 100 c . . . , prior to pixel sampling as shown in FIG. 5 . The precharge voltage V PRE that the supply circuit 475 provides for different imaging devices may vary depending on a number of factors; the main ones being the voltage of the voltage supply 150 of the imaging device 400 itself and the level of parasitic capacitance C ParP associated with the design of the imaging device 400 . The actual precharge voltage V PRE , which would normally always be less then the imaging device 400 voltage supply 150 voltage, can be readily determined by one skilled in the art. It has been found that typically for a 3.3 V imaging device 400 power supply 150 voltage V DD , an approximately 2.0 V precharge voltage V PRE is sufficient.

As a result of the application of the voltage V PRE to the line 100 a, ΔV A , shown in FIG. 5 as event 502 , is much reduced and is now is very similar to the voltage shift ΔV B shown as event 303 . This reduces the banding effect, which occurs in the first frame.

The present invention may be implemented by providing a separate voltage supply circuit 475 a, 475 b, 475 c . . . for each column 100 a, 100 b, 100 c . . . as shown in FIG. 6 . Each column 100 a, 100 b, 100 c . . . will have a switch 480 a, 480 b, 480 c . . . for selectively coupling it, under the control of a controller 485 , to the voltage supply circuit 475 a, 475 b, 475 c . . . , when its respective column sample circuit 295 a, 295 b, 295 c . . . is not connected through its switch 290 a, 290 b, 290 c . . . to the respective column line 100 a, 100 b, 100 c . . . .

In the embodiments shown in FIGS. 4 and 8 , only one precharge circuit 475 is used for the entire array of pixels 135 . In FIG. 4 , the precharge circuit 475 is selectively coupled to each column line 100 a, 100 b, 100 c . . . through a respective switch 480 a, 480 b, 480 c . . . controlled by controller 485 for each column 100 a, 100 b, 100 c . . . in the imaging device 400 . The precharge switch 480 a, 480 b, 480 c . . . would be opened, as the array 200 was about to be read when the coupling switch 290 connects the sampling circuit 295 a, 295 b, 295 c . . . to switch on and read the voltage on the respective column line 100 a, 100 b, 100 c . . . . Alternatively, as shown in FIG. 8 , the precharge circuit 475 is coupled to all of the columns 100 a, 100 b, 100 c . . . through a switch 480 controlled by controller 485 for all of the columns 100 a, 100 b, 100 c . . . for the array 800 .

Another embodiment of the present invention is shown in FIG. 7 . The imaging device 700 uses separate precharge circuits 475 475 a, 475 b, . . . for precharging pre-selected blocks of columns 100 a, 100 b, 100 c . . . in the array 200 . In this particular embodiment, though preselected blocks 701 , 701 , . . . are shown to include pairs of column 102 a with 102 b, 102 c with 102 d, . . . other arrangements are within the scope of the present invention. Each precharge circuit 475 a, 475 b, . . . would be selectively coupled to a respective block 701 , 702 , . . . through a switch 480 a, 480 b , . . . when the preselected columns 100 a, 100 b, 100 c . . . in the blocks 701 , 702 , . . . are not being sampled.

The precharging system may also be implemented by inserting of a voltage level detection circuit 490 on each of the column signal lines 100 a, 100 b, 100 c . . . as shown in FIG. 4 . Upon the detection of a voltage level on a signal line 100 a, 100 b, 100 c . . . that is far below a level where useful pixel data would exist, the column line 100 a, 100 b, 100 c . . . in question would be clamped to a precharge circuit 475 through a switching device 480 a, 480 b, 480 c . . . under the control of the controller 485 . This would minimize power use by not applying a precharge voltage when it is not required and at the same time allow the column signal line 100 a, 100 b, 100 c . . . to retain at least a minimal precharge voltage.

While the invention has been described according to what is presently considered to be the most practical and preferred embodiments, it must be understood that the invention is not limited to the disclosed embodiments. Those ordinarily skilled in the art will understand that various modifications and equivalent structures and functions may be to made without departing from the spirit and scope of the invention as defined in the claims. Therefore, the invention as defined in the claims must be accorded the broadest possible interpretation so as to encompass all such modifications and equivalent structures and functions.