Inverter circuit

1. Field of the Invention

The present invention relates to an inverter circuit, and more particularly to an inverter circuit supplying polyphase power.

2. Discussion of the Background

FIG. 20 is a circuit diagram showing a configuration of a background-art inverter circuit 1 a and connection of the circuit 1 a and peripheral devices. Terminals P and N on both ends of a smoothing capacitor 70 are connected to a not-shown electronic power rectifier which can employ a diode bridge and the like and supplied with substantially-direct current power therefrom. The inverter circuit 1 a converts the substantially-direct current power into three-phase electric power and supplies this power for a load 71 such as a motor M.

In the inverter circuit 1 a, on each “L” side of U-phase, V-phase and W-phase, i.e., on a side connected to the terminal N provided are IGBTs (Insulated Gate Bipolar Transistor: hereinafter, simply referred to as “transistor”) 20 F, 21 F and 22 F each with a protective diode for producing a regenerative current. On each “H” side of the U-phase, the V-phase and the W-phase, i.e., on a side connected to the terminal P provided are IGBTs 23 F, 24 F and 25 F each with the protective diode. Their The gates of the transistors 20 F, 21 F, 22 F, 23 F, 24 F and 25 F are connected to a controller 10 a, and specifically their operations are controlled by a driving circuit 12 included in the controller 10 a. Supplied with an overcurrent signal by an overcurrent protective circuit 11 , the driving circuit 12 controls the operations of the transistors so that no excess current may flow into the transistor in which an overcurrent possibly flows.

The possibility that an overcurrent flows in the transistor inverter can be detected as follows. Emitters of the transistors 20 F, 21 F and 22 F on the “L” side are connected in common to one end of a resistor 30 . A voltage drop caused by a current flowing in the resistor 30 is given to one input end of a comparator 13 through a low-pass filter 45 consisting of a resistor 47 and a capacitor 46 . The other input end of the comparator 13 is connected to a power supply 14 for supplying a predetermined voltage Vref. An output of the comparator 13 is given to the overcurrent protective circuit 11 . Therefore, when a current large enough to cause a voltage drop higher than the voltage Vref flows in the resistor 13 , judging that an overcurrent flows in at least one of the transistors 20 F, 21 F and 22 F, the overcurrent protecttive circuit 11 applies the overcurrent signal to the driving circuit 12 . For example, the driving circuit 12 receives the overcurrent signal to turn off the transistors 20 F, 21 F and 22 F.

Thus, the technique to detect an overcurrent by a DC bus detection system is disclosed in e.g., Japanese Patent Application Laid Open Gazette No. 7-298481.

FIG. 21 is a circuit diagram showing a configuration of another background-art inverter circuit 1 b and connection of the circuit 1 b and peripheral devices. As compared with the inverter circuit 1 a, the transistors 20 F, 21 F and 22 F on the “L” side are replaced by transistors 20 S, 21 S and 22 S each comprising a current detection terminal as well as the protective diode. The current detection terminals of the transistors 20 S, 21 S and 22 S are connected in common to the terminal N through resistors 30 u, 30 v and 30 w, respectively.

The inverter circuit 1 b comprises a controller 10 b. The controller 10 b has control units 10 u, 10 v and low 10 w corresponding to the respective phases, which control drivings of the transistors 20 S, 21 S and 22 S, respectively. For example, the control unit 10 u comprises a comparator 13 u, an overcurrent protective circuit 11 u and a driving circuit 12 u.

One input end of the comparator 13 u is connected to a power supply 14 u for supplying the voltage Vref, and the other input end receives a voltage drop across the resistor 30 u through a filter 45 u having the same constitution as the filter 45 connected to the inverter 1 a.

The overcurrent protective circuit 11 u gives overcurrent information to the driving circuit 12 u on the basis of an output from the comparator 13 u. For example, when the voltage drop across the resister 30 u is higher than the voltage Vref, judging that an ovecurrent flows in the transistors 20 S, the driving circuit 12 u given the overcurrent information from the overcurrent protective 11 u turns off the transistor 20 S. Similarly, the other control units 10 v and 10 w monitor voltage drops across the resistors 30 v and 30 w through filters 45 v and 45 w to control operations of the transistors 21 S and 22 S, respectively.

Thus, the technique to detect an overcurrent by phase-current detection system using transistors having current detection terminals is disclosed in e.g. Japanese Patent Application Laid Open Gazette No. 9-219976.

The background-art technique to detect an overcurrent by the DC bus detection system has a problem that a loss across the resistor 30 becomes larger since a current flowing in a bus connected to the transistors 20 F, 21 F and 22 F causes the voltage drop across the transistor resistor 30 . Further, as the resistor 30 , it is necessary to adopt a high-power resistor, so it disadvantageously costs high. Moreover, it is not easy to incorporate such a resistor in the inverter circuit 1 a and it is necessary to separately provide the resistor outside the inverter circuit 1 a.

The background-art technique to detect an overcurrent by the phase-current detection system has a problem that it is impossible to reduce the size of the inverter circuit 1 b since the respective current detection terminals of the transistors 20 S, 21 S and 22 S are connected to the controller 10 b to increase the number of interconnection lines. Further, in order to transfer the voltage drops across the resistors 30 u, 30 v and 30 w to the control units 10 u, 10 v and 10 w while avoiding an effect of noise, it is necessary to provide the filters 45 u, 45 v and 45 w corresponding to the respective phases.

An object of the present invention is to solve the above problems by reducing the resistor losses and the number of resistors for overcurrent detection and decreasing the number of filters.

The first aspect of an inverter circuit in accordance with the present invention is characterized in that the inverter connected to first and second terminals which are given a substantially-direct current and supplying polyphase power comprises: a plurality of switching elements on a first side, each including a first end connected to the first terminal, a second end and a regenerative current element provided between the first and second ends; a plurality of switching elements on a second side, each including a first end, a second end connected to the second terminal, a regenerative current element provided between the first and second ends thereof and a current detection terminal for detecting a current flowing therein; a resistive device developing a voltage drop by a sum of currents flowing in the second ends current detection terminals of the plurality of switching elements on the second side; and a driving circuit for controlling a driving operation on the plurality of switching elements on the second side on the basis of a comparison result between the voltage drop and a predetermined voltage, and the second ends of the plurality of switching elements on the first side and the first ends of the plurality of switching elements on the second side are connected to output the polyphase power.

The second aspect of the inverter circuit in accordance with the present invention is the first aspect of the inverter circuit, which is characterized in that the resistive device and the driving circuit are integrated.

The third aspect of the inverter circuit in accordance with the present invention is the first aspect of the inverter circuit, which is characterized in that the resistive device is integrated with at least one of the plurality of switching elements on the second side.

The fourth aspect of the inverter circuit in accordance with the present invention is the third aspect of the inverter circuit, which is characterized in that the resistive device is integrated with one of the plurality of switching elements on the second side.

The fifth aspect of the inverter circuit in accordance with the present invention is the third aspect of the inverter circuit, which is characterized in that the resistive device consists of a plurality of resistive elements connected in parallel as many as the plurality of switching elements on the second side, and the plurality of resistive elements are integrated with the plurality of switching elements on the second side, respectively.

The sixth aspect of the inverter circuit in accordance with the present invention is the first aspect of the inverter circuit, which is characterized in that the inverter circuit further comprises: a comparator for comparing the voltage drop with the predetermined voltage.

The seventh aspect of the inverter circuit in accordance with the present invention is the sixth aspect of the inverter circuit, which is characterized in that the inverter circuit further comprises: a filter for giving the voltage drop with noise cut to the comparator.

The eighth aspect of the inverter circuit in accordance with the present invention is the seventh aspect of the inverter circuit, which is characterized in that the filter is integrated with the comparator.

The ninth aspect of the inverter circuit in accordance with the present invention is the seventh aspect of the inverter circuit, which is characterized in that the filter is integrated with the driving circuit.

The tenth aspect of the inverter circuit in accordance with the present invention is the sixth aspect of the inverter circuit, which is characterized in that the inverter circuit further comprises: a power supply, and the predetermined voltage is divided by second and third resistive devices and applied to the comparator.

The eleventh aspect of the inverter circuit in accordance with the present invention is the tenth aspect of the inverter circuit, which is characterized in that the second and third resistive devices are integrated with the comparator.

The twelfth aspect of the inverter circuit in accordance with the present invention is the tenth aspect of the inverter circuit, which is characterized in that the second resistive device is externally provided.

The thirteenth aspect of the inverter circuit in accordance with the present invention is the twelfth aspect of the inverter circuit, which is characterized in that the resistance value of the second resistive device is variable.

The fourteenth aspect of the inverter circuit in accordance with the present invention is the twelfth aspect of the inverter circuit, which is characterized in that the third resistive device is externally provided.

In the inverter circuit of the first to sixth aspects of the present invention, since it is possible to adopt a resistor whose loss is smaller than the resistor adopted in the technique to detect the overcurrent by the background-art DC bus detection system, the resistor of the present invention can be integrated together with other elements.

In the inverter circuit of the seventh to ninth aspects of the present invention, the interconnection is simpler than that in the technique to detect the overcurrent by the background-art phase-current detection system and only one filter is needed to defend the voltage drop reflecting the overcurrent against noise. Therefore the filter 45 can be also integrated together with other elements.

In the inverter circuit of the tenth and eleventh aspects of the present invention, it is possible to appropriately set a reference voltage for the voltage drop reflecting the overcurrent.

In the inverter circuit of the twelfth to fourteenth aspects of the present invention, it is possible to externally control the reference voltage.

A more complete appreciation of the present invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein,

FIG. 1 is a circuit diagram showing a configuration of an inverter circuit in accordance with a first preferred embodiment of the present invention;

FIGS. 2 to 15 are circuit diagrams showing an operation of the inverter circuit in accordance with the first preferred embodiment of the present invention;

FIG. 16 is a circuit diagram showing a configuration of an inverter circuit in accordance with a second preferred embodiment of the present invention;

FIG. 17 is a circuit diagram showing a configuration of an inverter circuit in accordance with a third preferred embodiment of the present invention;

FIG. 18 is a circuit diagram showing a configuration of an inverter circuit in accordance with a fourth preferred embodiment of the present invention;

FIG. 19 is a circuit diagram showing a configuration of an inverter circuit in accordance with a fifth preferred embodiment of the present invention; and

FIGS. 20 and 21 and are circuit diagrams showing configurations of inverter circuits in the background art.

The First Preferred Embodiment

FIG. 1 is a circuit diagram showing a configuration of an inverter circuit 1 c in accordance with the first preferred embodiment of the present invention. The terminals P and N on the both ends of the smoothing capacitor 70 are connected to a not-shown electronic power rectifier which can employ a diode bridge and the like and supplied with substantially-direct curent power therefrom. The inverter circuit 1 c converts this substantially-direct current power into three-phase electric power and supplies this power for the load 71 such as the motor M.

In the inverter circuit 1 c, on each “L” side of U-phase, V-phase and W-phase provided are the transistors 20 S, 21 S and 22 S each with a protective diode and a current detection terminal. On each “H” side of U-phase, V-phase and W-phase provided are the transistors 23 F, 24 F and 25 F each with a protective diode. In respective phases, the tansistors 20 S and 23 F, the transistors 21 S and 24 F and the transistors 22 S and 25 F are connected in series to each other between the terminals P and N. Specifically emitters of the transistors 20 S, 21 S ad 22 S are connected in common to the terminal N and collectors of the transistors 23 F, 24 F and 25 F are connected in common to the terminal P.

The U-phase of the load 71 is connected to a node between a collector of the transistor 20 S and an emitter of the transistor 23 F, the V-phase of the load 71 is connected to a node between a collector of the transistor 21 S and an emitter of the transistor 24 F and the W-phase of the load 71 is connected to a node between a collector of the transistor 22 S and an emitter of the transistor 25 F.

TheirThe gates of the transistors 20 S, 21 S, 22 S, 23 F, 24 F and 25 F are connected to a controller 10 c, and specifically their operations are controlled by the driving circuit 12 included in the controller 10 c.

In the controller 10 c, one end of a resistor 30 s is connected to the terminal N and the other end is connected to the current detection terminals of the tansistors 20 S, 21 S and 22 S. A voltage drop across the resister 30 s is cleared of noise by the filter 45 and given to one input end of the comparator 13 , the filter 45 is a low-pass filter, and can be easily constituted of the resistor 47 and the capacitor 46 , for example, as shown in FIG. 20 .

The other input end of the comparator 13 is given a voltage obtained by dividing the voltage Vref supplied from the power supply 14 by resistors 34 and 35 as a reference voltage. The overcurrent protective circuit 11 gives the overcurrent information to the driving circuit 12 on the basis of the output of the comparator 13 . The driving circuit 12 controls the operation of the transistors on the basis of the overcurrent information.

When an overcurrent flows in any one of the transistors 20 S, 21 S and 22 S, a large current corresponding to the overcurrent is carried to the resistor 30 s from the current detection terminal of the transistor in which the overcurrent flows. Since the current flowing in the resister 30 s is smaller than that in the technique to detect the overcurrent by the background-art DC bus detection system, however, the loss is smaller and it is not necessary to adopt a high-power resistor. Therefore, it is possible to incorporate the resistor 30 s in the controller 10 c, or further to integrate the controller 10 c on the whole. To detect that the overcurrent flows in the transistors 20 S, 21 S and 22 S by the voltage drop across the resistor 30 s, the reference voltage obtained by dividing the voltage Vref by the resistors 34 and 35 is given to the comparator 13 .

As compared with the technique to detect the overcurrent by the background-art phase-current detection system, since the respective current detection terminals of the transistors 20 S, 21 S and 22 S are in common to the controller 10 c, the interconnection is not complicated and only one filter 45 is needed to suppress noise. Therefore, the filter 45 can be also incorporated in the controller 10 c, or further the controller 10 c can be integrated on the whole.

Supplied with the overcurrent signal from the overcurrent protective circuit 11 , the driving circuit 12 controls the operations of the transistors so that no current may flow into the transistor in which the overcurrent possibly flows. For example, the driving circuit 12 turns off all the transistors 20 S, 21 S and 22 S.

FIGS. 2 to 4 are circuit diagrams showing one of operation patterns in accordance with this preferred embodiment of the present invention. In FIGS. 2 to 4 , the controller 10 c is omitted. Broken lines represent flows of a current. It is assumed that the amount of current which can flow in the transistor in each of the phases is 25 amperes maximum. Accordingly, when a current over 25 amperes flows in any one of the transistors, an overcurrent flows in the transistor.

FIG. 2 shows a case where a current flows from the U-phase to the V-phase and W-phase and a current separately flows into the transistors 21 S and 22 S from the transistor 23 F throught the load 71 . When a current of 15 amperes flows in each of the transistors 21 S and 22 S, an overcurrent of 30 amperes flows in the transistor 23 F. In this case, the current of 30 amperes flows in the resistor 30 s of the controller 10 c shown in FIG. 1 , across which the voltage drop is large, and the driving circuit 12 turns off all the tansistors 20 S, 21 S and 22 S with the overcurrent. In other words, monitoring only the transistors on the “L” side makes it possible to detect that the overcurrent flows in the transistors on the “H” side.

FIG. 3 shows a case where the driving of the transistors on the “H” side is kept after the overcurrent flows in the transistor 23 F, and FIG. 4 shows a case where all the transistors on the “H” side are also turned off. A regenerative current flows through the transistors 23 F, 24 F and 25 F (exactly, the protective diode of the transistor 25 F 24 F) and 25 F ( exactly, the protective diode of the transistor 25 F ) on the “H” side in the case of FIG. 3 , and through the respective protective diodes of the transistors 20 S, 24 F and 25 F in the case of FIG. 4 .

FIGS. 5 to 7 are circuit diagrams showing another operation pattern in accordance with this preferred embodiment of the present invention, and use the same representation as FIG. 2 . FIG. 5 shows a case where a current flows from the U-Phase and V-phase to the W-phase, and further through the transistors 23 F and 24 F and then the load 71 to the transistor 22 S. When a current of 15 amperes flows in each of the transistors 23 F and 24 F, an overcurrent of 30 amperes flows in the transistor 22 S. Also in this case, naturally, the driving circuit 12 can turn off all the transistors 20 S, 21 S and 22 S.

FIG. 6 shows a case where the driving of the transistors on the “H” side is kept after the overcurrent flows in the transistor 22 S, and FIG. 7 shows a case where all the transistors on the “H” side are also turned off. A regenerative current flows tghfough the transistors 23 F, 24 F and 25 F on the “H” side in the case of FIG. 6 , and through the respective protective diodes of the transistors 20 S, 21 S and 25 F in the case of FIG. 7 .

FIGS. 8 to 12 are circuit diagrams showing still another operation pattern in accordance with this preferred embodiment of the present invention, and use the same representtion as FIG. 2 . Both FIGS. 8 and 9 show a case where a partial short circuit is caused between the U-phase and the V-phase. FIG. 8 shows a case where a current flows from the U-phase to the V-phase and W-phase; and FIG. 9 shows a case where a current flows from the U-phase and V-phase to the W-phase. FIGS. 10 and 11 show two cases of short circuits between the U-phase and the V-phase (a short circuit inside the load 71 i.e., an arm-windings-short, and a short circuit between terminals connecting the load 71 and the inverter 1 c, i.e., a terminals-short). FIG. 12 shows a short circuit inside the inverter 1 c, i.e., an arm-short-through.

In the case of FIGS. 8 and 9 , the load 71 is substantially a non-equilibrium load. In FIG. 8 , even if currents of 10 amperes and 20 amperes flow in the transistors 21 S and 22 S, respectively, for example, and the respective amounts of currents flowing in the transisors 21 S and 22 S are appropriate, a current flowing in the transistors 21 S and 22 S are appropriate,a current flowing in the transistor 23 F is 30 amperes. In such a case, like in the case of FIG. 2 , it is possible to detect that the overcurrent flows in any one of the transistors and turn off, for example, all the transistors at least on the “L” side. Similarly, in the case of FIG. 9 for example, when currents of 20 amperes and 10 amperes flow in the transistors 23 F and 24 F, respectively, and a current flowing in the transistor 22 S is 30 amperes, it is naturally possible to perform such a control as to turn off the transistor 22 S.

In both the cases of FIGS. 10 and 11 , since overcurrents flow in the transistors 23 F and 21 S equally, it is possible to perform such a control as to turn off the transistor 21 S. In the case of FIG 12 , since overcurrents flow in the transistors 23 F and 20 S equally, it is possible to perform such a control as to turn off the transistor 20 S.

FIGS. 13 to 15 show a case where the U-phase in the load 71 is ground-shorted. FIGS. 13 and 14 show a case where the U-phase part of the load 71 is partially ground-shorted through a case of the load 71 , and FIG. 15 shows a case where the U-phase part of the load 71 is directly ground-shorted. FIG.13 shows a case where a current flows from the U-phase to the V-phase and W-phase, and FIG. 14 shows a case where a current flows from the U-phase and V-phase to the W-phase.

In these cases, unfortunately, failures can not be always detected. That is because part of the overcurrent flows to the ground due to the ground short and the current flowing in the resistor 30 s in the controller 10 c does not reflect the sum of the currents flowing in the transistors on the “L” side or the sum of the currents flowing in the transistors on the “H” side. For example, to FIG. 13 , even when a current of 30 amperes flows in the transistor 23 F, if a ground-short current of 10 amperes flows, the sum of the currents flowing in the transistors 21 S and 22 S is 20 amperes and therefore it is impossible to detect that an overcurrent is produced. Further, in FIG. 14 , when the ground-short current is 10 amperes, even if the sum of the currents flowing in the transistors 23 F and 24 F is 30 amperes, only a current of 20 amperes flows in the transistor 22 S and no overcurrent is produced, and therefore it is imposible to detect a ground short. Furthermore, in FIG. 15 , when an overcurrent flows in the transistor 23 F on the “H” side, if the whole current flows into the ground, no current flows in any transistor on the “L” side and therefore it is impossible to detect that an overcurrent is produced.

The difficulty in failure detection due to the existence of ground-short current is, however, not specific to the configuration of the present invention and is found in the technique to detect an overcurrent by the DC bus detection system. In other words, the configuration of the present invention does not inevitably cause a faulty operation which has not been caused in the background art.

The Second Preferred Embodiment

FIG. 16 is a circuit diagram showing a configuration of an inverter circuit id 1 d in accordance with the second preferred embodiment of the present invention. As compared with the inverter circuit 1 c of FIG. 1 , the transistors 20 S, 21 S and 22 S are replaced by transistors 20 T, 21 T and 22 T, respectively. Further, the controller 10 c is replaced by a controller 10 d, and the controller 10 d has a configuration in which the resistor 30 s is removed from the controller 10 c.

The transistors 20 T, 21 T and 22 T have configurations in which the resistors 30 u, 30 v and 30 w are additionally incorporated in the transistors 20 S, 21 S and 22 S, respectively. The resistors 30 u, 30 v and 30 w are interposed between current detection terminals of the transistors 20 T, 21 T and 22 T and the terminal N. Therefore, equivalently, it can be considered that the resistor 30 s is replaced by a parallel connection of the three resistors 30 u, 30 v and 30 w.

As discussed in the first preferred embodiment, the loss across the resistor 30 s is not larger than smaller than that of the resistor 30 in the background art as shown in FIG. 20 . Therefore, the resistors 30 u, 30 v and 30 w can be integrated together with the transistors 20 T, 21 T and 22 T.

Configured as above, this preferred embodiment produces an effect of making the configuration of the controller 10 d simpler than that of the controller 10 c as well as the effect of the first preferred embodiment.

The Third Preferred Embodiment

FIG. 17 is a circuit diagram showing a configuration of an inverter circuit 1 e in accordance with the third preferred embodiment of the present invention. As compared with the inverter circuit 1 d of FIG. 16 , the transistors 21 T and 22 T are replaced by the transistors 21 S and 22 S, respectively. Therefore, as compared with the inverter circuit 1 c of the first preferred embodiment, it can be considered that the resistor 30 s is incorporated in the transistor 20 T as the resistor 30 u. It is obvious that this configuration produces the effect of the second preferred embodiment.

The Fourth Preferred Embodiment

FIG. 18 is a circuit diagram showing a configuration of an inverter circuit 1 f in accordance with the fourth preferred embodiment of the present invention. As compared with the inverter circuit 1 c of FIG. 1 , the controller 10 c is replaced by a controller 10 f and the controller 10 f has a configuration in which the power supply 14 and the resistors 34 and 35 are removed from the controller 10 c.

Instead of the removed power supply 14 and resistors 34 and 35 , variable resistors resistor 40 and resistor 41 for dividing a voltage supplied from an external power supply 15 and applying the divided voltage to the comparator 13 are provided outside the inverter circuit 1 f.

Thus, supplying a reference voltage for overcurrent detection from the outside of the controller 10 f allows an additional advantage that the above reference voltage can be externally controlled by the variable resistor 40 according to the characteristics of the inverter circuit if 1 f even if the controller 10 f is integrated.

It is natural that also in the first to third preferred embodiments, it is possible to adapt the reference voltage to the characteristics of the inverter circuits 1 c to 1 e by appropriately setting the resistance values of the resistors 34 and 35 .

The Fifth Preferred Embodiment

FIG. 19 is a circuit diagram showing a configuration of an inverter circuit 1 g in accordance with the fifth preferred embodiment of the present invention. As compared with the inverter circuit 1 c of FIG. 1 , the controller 10 c is replaced by a controller 10 g and the controller 10 g has a configuration in which the resistor 35 is removed from the controller 10 c.

Instead of the removed resistor 35 , the varible resistor 40 is provided outside the inverter circuit 1 g, and the voltage Vref supplied from the power supply 14 is divided by the resistor 34 and the variable resistor 40 and applied to the comparator 31 .

Thus, providing the variable resistor 40 for controlling the reference voltage for overcurrent detection outside the control circuit log allows an additional advantage that the above reference voltage can be controlled according to the characteristics of the inverter circuit 1 g even if the controller 10 g is integrated.

Further, it is natural that it is possible to combine the first the third preferred embodiments with the contents of the fourth and fifth preferred embodiments.

While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.