Semiconductor memory device for use in apparatus requiring high-speed access to memory cells

This application is a continuation of application Ser. No. 07/905,416, filed Jun. 29, 1992, now abandoned.

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for use with apparatuses requiring high speed access to memory cells.

FIG. 1 is a block diagram showing a conventional semiconductor integrated circuit FIG. 1, memory cells (MC) 3 are selected by a word line 2, and one of them is accessed by complementary bit lines L Bit lines 1 are connected to column switches 5 which are turned on/off by a column switch control (CC) signal 4. Each memory cell 3 is connected to bit lines 1 and a word line 2 as shown in the circuit diagram of FIG. 2. One of memory cells 3 selected by the word line 2 is accessed by the bit lines 1.

The circuit arrangement shown in PIG. 1 is generally called a word line control system. With this system, when one word line 2 is selected, all memory cells 3 connected to this word line 2 are activated Therefore, there arises the problem of a large load and hence large consumption current.

A circuit eliminating the above problem is known which has the structure as shown in FIG. 3. In this circuit, memory cells are divided into blocks of several memory cell array sections 9. An access signal from a main word line 6 is selected by using a section select line 8, and connected to a section word line 7 provided for each array section 9. As shown in the block diagram of FIG. 4, in each array section 9, a NOR gate executes a logical operation between signals on the main word line 6 and the section select line 8, to select a particular section word line 7. Memory cells 3 selected by the section word line 7 are being disposed in a similar manner as shown in FIG. 1. Each memory cell 3 is accessed by controlling column switches connected to the bit lines 1 upon reception of a column switch control signal 4.

With the above-described arrangement, the section word line 7 in each memory cell array section 9 is selected in accordance with the logical condition between the main word line 6 and section select line 8. Memory cells 3 connected only to the selected section word line 7 are activated, allowing reduced load and consumption current.

Conventional semiconductor integrated circuits have been structured in the manner just described above. Therefore, in order to select a particular one of section word lines 7 of each array section 9, it is necessary to provide logical circuits for obtaining logical conditions between the main word line 6 and section selection lines 8. These logical circuits are connected to the section select lines 8, posing another problem of a large load on the section selection line 8. The section select line 8 is usually connected to the gates of transistors each of which outputs a select signal to the corresponding section word line 7. However, the gate capacitance of such a transistor is substantially large, and the select speed is lowered essentially. Particularly in the case where the section select line 8 is driven by a CMOS inverter, the load becomes excessively heavy, resulting in a low access speed.

The present invention has been made in consideration of the above-described circumstances. It is an object of the present invention to provide a semiconductor memory device allowing a high speed access to memory cells, by obtaining a signal to be supplied to the gate of a transistor driving each section word line, from a BiCMOS inverter with a large drive current capacity.

According to the present invention, a logical circuit executes a logical operation of signals on a main word line and a section select line. An output from the logical circuit selects a particular section word line of each array section. In each logical circuit, the section select line is not directly connected to the gate of a transistor. Therefore, a load of the section select signal is small.

Furthermore, a section select signal supplied to each section select line is obtained from a BiCMOS inverter, at a speed higher than that when the section select signal is obtained from a CMOS inverter. A lowered high level output of the BiCMOS inverter is raised to a power source voltage V CC by a P-channel transistor, and a degraded discharge speed can be prevented by using a delay circuit.

As described above, according to the present invention, in a semiconductor memory device whose memory cells are divided into a plurality of memory cell array sections, a section word line in each array section is selected by a main word line and section select line, without directly connecting the section select line to the gate of a transistor connected to the section word line, thereby reducing the load. Furthermore, a BiCMOS structure is used for driving a section select line, improving a drive power and realizing high speed memory access.

FIG. 1 is a block diagram showing a conventional semiconductor memory device.

FIG. 2 is a circuit diagram showing connections of a memory cell shown in FIG. 1 to a word line and bit lines.

FIG. 3 is a block diagram showing another conventional semiconductor memory device.

FIG. 4 is a circuit diagram showing the structure of a memory cell array section shown in FIG. 3.

FIG. 5 is a block diagram showing the outline of a first embodiment according to the present invention.

FIG. 6 is a circuit diagram showing the internal structures of the memory cell array section and the first circuit shown in FIG. 5.

FIG. 7 is a circuit diagram showing an example of the second circuit shown in FIG. 5.

FIG. 8 is a circuit diagram showing another example of the second circuit shown in FIG. 5.

FIG. 9 is a circuit diagram showing another example of the second circuit shown in FIG. 5.

FIG. 10 is a circuit diagram showing examples of the inverts Inv 1 and Inv 2 shown in FIG. 6.

Preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 5 is a block diagram showing a semiconductor memory device according to the present invention. As shown in FIG. 5, a main word line 6 and section select lines 8 are connected to a first circuit 11. A section word line 7 extends out of the first circuit 11. The section select lines 8 extend out of second circuit 12.

FIG. 6 is a detailed circuit showing part of the device, i.e., the internal circuit of the cell array section 9 and first circuit 11. As seen from FIG. 6, the man word line 6 is connected to first and second inverters Inv 1 and Inv 2 of the first circuit 11. The section select line 8 is connected to the drain of an N-type transistor 14 and the source of a P-type transistor constituting the second inverter Inv 2 (refer to FIG. 10). The gate of the N-type transistor 14 is connected to the output of the inverter Inv 1, and the source thereof is connected to the section word line 7. The output terminal of the inverter Inv 2 is connected to the section word line 7. Each section select line 8 is, therefore, not connected directly to the gates of the transistors driving the section word line 7, thereby providing a very small load. The detailed circuit of the inverters Inv 1 and Inv 2 is shown in FIG. 10.

The operation will be described. It is assumed that the main word line 6 follows negative logic, and the section select line 8 follows positive logic. Namely, the section word line 7 is activated to a high level when the main word line 6 takes a low level and the section select line 8 takes a high level. It is to be noted that the section select line 8 is not connected to the gate of the transistor used for driving the section word line 7. Therefore, it is possible to provide a very small load and a high speed access.

FIG. 7 is a detailed circuit diagram showing an example of the second circuit 12 which outputs a section select signal to the section select line 8. A signal IN inputted for section selection is inverted by a BiCMOS inverter 10, and outputted onto the section select line 8. An output from the BiCMOS inverter 10 takes a level V B1 or (V CC -V B1 ) where V CC is a power source voltage and V B1 is a saturation voltage. A high level output at the BiCMOS inverter is lowered by V B1 . In order to raise the high level output to V CC , the section select line 8 is connected to the gate of a P-channel transistor Pch via an inverter 15, the source of the transistor Pch being connected to the power source voltage V CC .

The operation of the second circuit constructed as shown in FIG. 7 will be described under the condition that an output of the BiCMOS inverter 10 takes a low level. In this case, a high level is applied to the gate of the P-channel transistor Pch via the inverter 15, thereby maintaining the P-channel transistor Pch to turn off and the section select line 8 to be set to the low level (=V B1 ). Under this state, when the output of the BiCMOS inverter 10 changes to the high level, a low level is applied to the gate of the P-channel transistor Pch via the inverter 15, thereby turning on the transistor Pch. The section select line 8 is thus connected to the power source voltage V CC and raised to this level V CC .

Alternatively, when the output of the BiCMOS inverter 10 changes from the high level to the low level, the BiCMOS inverter 10 operates to discharge the section select line 8, and at the same time turns off the P-channel transistor Pch via the inverter 15, allowing to continue the discharge of the section select line 8.

FIG. 8 is a circuit diagram showing another example of the second circuit for outputting a select signal to the section select line 8. This example provides an improved discharge speed when an output of the BiCMOS inverter 10 changes from the high level to the low level. As shown in FIG. 8, a signal IN inputted for section selection is inverted by a BiCMOS inverter 10, and outputted onto the section select line 8. In order to raise the output high level of the BiCMOS inverter 10 to the level V CC , there is provided a first P-channel transistor Pch 1 whose source is connected to the power source voltage V CC and whose gate is inputted with a signal level on the section select line 8 inverted by an inverter 15. The drain of a first P-channel transistor Pch 1 is connected to the source of the second P-channel transistor Pch 2 whose drain is connected to the section select line 8. The gate of the second P-channel transistor Pch 2 is connected to the output terminal of a delay circuit 13 having a plurality stage of inverters for delaying an output of the BiCMOS inverter 10.

Next, the operation of this second circuit will be described. First, while the output of the BiCMOS inverter 10 takes the low level, the first and second P-channel transistors Pch 1 and Pch 2 are being turned off/on, respectively. The section select line 8 is therefore taking the low level (=V B1 ). In this state, when the output of the BiCMOS inverter 10 changes to the high level, the gate of the first P-channel transistor Pch 1 takes the low level and turns on. However, the delay circuit 13 keeps the gate of the second P-channel transistor Pch 2 at the low level. Therefore, the section select line 8 is connected to the power source voltage V CC and raised to this level V CC . Thereafter, a signal delayed by the delay circuit 13 is applied to the gate of the second P-channel transistor Pch 2 which is then turned off by this signal applied to its gate. At this time, the section select line 8 enters a floating state and holds the V CC level. Alternatively, when the output of the BiCMOS inverter 10 changes from the high level to the low level, the first P-channel transistor Pch 1 immediately turns off, and the second P-channel transistor Pch 2 turns on after the delay time of the delay circuit 13. As a result, the section select line 8 discharges rapidly.

FIG. 9 is a circuit diagram showing another example of the second circuit 12 for outputting a section select signal to the section select line 8. In this example, one P-channel transistor is used for charging the section select line 8 up to the V CC level. As shown in FIG. 9, a signal IN inputted for section selection is inverted by a BiCMOS inverter 10, and outputting onto the section select line 8. In order to raise the output high level of the BiCMOS inverter 10 to the level V CC , there is provided a P-channel transistor Pch whose source is connected to the power source voltage V CC and whose gate is inputted with an output of a logical gate 16. This logical gate 16 is inputted with an output of the BiCMOS 10 and an output of a delay circuit 13 having a plurality stage of inverters, the delay circuit 13 delaying the output of the BiCMOS inverter 10. A NAND operation between both the inputs is applied to the gate of the P-channel transistor Pch.

In operation of this second circuit constructed as above, while the output of the BiCMOS inverter 10 takes the low level, the output of the delay circuit 13 is taking the low level and so the output of the logical gate 16 is taking the high level. With the high level applied to the gate of the P-channel transistor Pch, it is maintained turned off. The section select line 8 is therefore taking the low level (=V B1 ). In this state, when the output of the BiCMOS inverter 10 changes to the high level, one input to the logical gate changes to the high level while maintaining the other input from the delay circuit 13 at the high level. The P-channel transistor Pch takes the low level at its gate and turns on. Therefore, the section select line 8 is connected to the power source voltage V CC and raised to the V CC level. On the other hand, while the output of the BiCMOS inverter 10 takes the high level, one input to the logical gate 16 is maintained to the low level of the output of the inverter 10 delayed by the delay circuit 13, and so the output of the logical gate 16 is maintained at the high level. With the high level gate input, the P-channel transistor Pch is being turned off. During this period, the section select line 8 enters the floating state and holds the V CC level. In this state, when the output of the BiCMOS inverter 10 changes from the high level to the low level, this second circuit operates as follows. The output of the logical gate 16 immediately takes the high level upon reception of the output from the BiCMOS inverter 10, and so the P-channel transistor Pch immediately turns off. The other input to the logical gate 16 takes the high level after the delay time of the delay circuit 13. However, the output state of the logical gate 16 will not change, so that the section select line 8 discharges rapidly.

As stated above, the section selection line 8 is not connected to the gate of a transistor so that the load of the section select line 8 is only a junction capacitor, the load being reduced by an amount corresponding to the gate capacitor. In the conventional circuit shown in FIG. 4, the section select line 7 is charged through two small size P-channel transistors of the logical circuit NOR. In contrast, in the circuit shown in FIG. 6 for example, the section select line 8 is charged through the bi-polar transistor of the BiCMOS inverter of the second circuit 12 and the small P-channel transistor Pch of the inverter Inv 2 connected to the section word line 7. The circuit of the present invention can therefore provide a faster charge speed.

In the embodiment shown in FIG. 5 for example, the first circuit 1 is used in common for both the right and left memory cell arrays 9, 9. Namely, shown in FIG. 10, a single inverter Inv 1 for inverting the select signal on the main word line 6 is used for both the arrays, to reduce the number of transistors.

Furthermore, the section word line 7 is connected to the sources of the transistor 14 and the connecting middle point of the inverter Inv. 2, so that the diffusion layer can be used in common for both the logical circuits, thereby allowing to implement the invention circuit on a semiconductor chip with substantially the same area as conventional, irrespective of that the invention circuit is somewhat complicated.

In the second circuit 12 connected to the section select line 8, the BiCMOS inverter 10 allows a high speed discharge of the section select line when the output of the BiCMOS inverter 10 changes from the high level to the low level.

Still further, a P-channel transistors used for charging the section select line 8 to V CC , and the output of the BiCMOS inverter 10 is used as an input signal to the P-channel transistor. Therefore, it is possible to set a potential of the section select line 8 at Vcc similarly as in the case where an output is obtained from a CMOS.