Combined input and output module
Granted 1 Jan 2019 · 4 office actions
Assignee: PILZ GMBH & CO. KG
Law firm: Law firm · Log in to unlock
Attorney: Attorney · Log in to unlock
Inventors: Lydia Wegerer, Markus Cech, Andreas Bell · Examiner: Cynthia Ramirez · AU 2924 · TC 2900
Life of the patent
9 dated eventsDescription
1 parts›FIG. 1 is a perspective view of the…
FIG. 1 is a perspective view of the combined input and output module embodying our new design;
FIG. 2 is a top view of the combined input and output module shown in FIG. 1 ;
FIG. 3 is a front view of the combined input and output module shown in FIG. 1 ;
FIG. 4 is a rear view of the combined input and output module shown in FIG. 1 ;
FIG. 5 is a left side view of the combined input and output module shown in FIG. 1 ;
FIG. 6 is a right side view of the combined input and output module shown in FIG. 1 ; and,
FIG. 7 is a bottom view of the combined input and output module shown in FIG. 1 .
The broken lines in the figures are for the purpose of illustrating portions of the combined input and output module that form no part of the claimed design.
Claims
1 · 1 independent · depth 1Classifications
1 codesClaim changes
SoonSee which claims were amended, added or cancelled during examination, with every added and removed word marked.
The published claims of this patent are not paired with the granted ones in what we hold.
File wrapper
See the full prosecution history — every USPTO and applicant action on this file, in order.
Log in to unlockChain of title
See the full assignment history — every owner this patent has passed through, with recordation dates and reel/frame numbers.
Log in to unlockTerm & fees
See the term timeline — pendency span, in-force span, the maintenance fees paid and both computed expiry dates.
Log in to unlockWorldwide family
2 members · 2 offices›IP5 & PCT — 2 members
| Office | Publication | Kind | Published | Filed | Status | Title |
|---|---|---|---|---|---|---|
| USthis patent | US-D837152-S | S1 | 1 Jan 2019 | 4 Aug 2016 | granted | Combined input and output module |
| JP | JP-1572748-S | S | 27 Mar 2017 | 4 Aug 2016 | granted | no title held |
Validity challenges
See the validity challenges on record — reexaminations, IPRs and PGRs, with their institution decisions and outcomes.
Log in to unlockCitations
See every patent this one cites and every patent that cites it back — publication, assignee, and how each one was found.
Log in to unlock