USPatentGranted
S1

Wafer carrier with a 31-pocket configuration

Granted 8 Aug 2017 · no office action yet

Current assignee: HSBC BANK USA, NATIONAL ASSOCIATION · originally Veeco Instruments

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Inventors: Keng Moy, Sandeep Krishnan · Examiner: Kevin Rudzinski · AU 2921 · TC 2900

Application
29/522,214
filed 27 Mar 2015
Publication
Not published
not published
Patent· this page
US D793972
granted 8 Aug 2017

Life of the patent

2 dated events
⤢ drag to zoomApr 2015Jul 2015Oct 2015Jan 2016Apr 2016Jul 2016Oct 2016Jan 2017Apr 2017Jul 2017Oct 2017Prosecution
Prosecutionhover for detail · click to open

Description

1 parts
›FIG. 1 is a perspective view of a…

FIG. 1 is a perspective view of a wafer carrier with a 31-pocket configuration according to the new design of the first embodiment.

FIG. 2 is a top plan view of a wafer carrier with a 31-pocket configuration according to the new design thereof.

FIG. 3 is a right side view of a wafer carrier with a 31-pocket configuration according to the new design, with the left side, front, and rear views being the same as the right side view thereof.

FIG. 4 is a bottom plan view of a wafer carrier with a 31-pocket configuration according to the new design thereof.

FIG. 5 is a perspective view of a wafer carrier with a 31-pocket configuration according to the new design of the second embodiment.

FIG. 6 is a right side view of a wafer carrier with a 31-pocket configuration according to the new design, with the left side, front, and rear views being the same as the right side view thereof.

FIG. 7 is a bottom plan view of a wafer carrier with a 31-pocket configuration according to the new design thereof; and,

FIG. 8 is a detail view of a portion of the wafer carrier with a 31-pocket configuration shown in FIG. 1 according to the new design showing a single pocket from a perspective view of the first embodiment.

The broken lines, where present, in FIGS. 1, 2, 3, 4, and 8 , illustrate portions of the wafer carrier with a 31-pocket configuration that represent environment of the claimed design and form no part of the claimed design. The broken lines of FIG. 1 that define the area corresponding to the enlarged portion shown in FIG. 8 form no part of the claimed design. The broken lines in FIG. 8 that represent the edge of the enlarged portion of the design form no part of the claimed design.

the grant prints no section headings; every part label below is ours, taken from that part's own first words

Claims

1 · 1 independent · depth 1
1 granted claims

Classifications

6 codes
IPC · International Patent Classification
Section H — Electricity
  • H10P72/10
  • H10P14/22
  • H10P14/24
USPC · US Patent Classification
D13/182D23/386D23/499

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File wrapper

Pendency
2.4 y
865 days filing → grant
Office actions
0
none on record
Examiner
Kevin Rudzinski
art unit 2921 · TC 2900
Citations: 244 back · 0 forward

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Chain of title

⤢ drag to zoom20162018202020222024202620282030203220342036Owner 1liens, releases & corrections
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Term & fees

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Worldwide family

6 members · 5 offices
US1JP1KR1DE1TW2
this patentIP5 & PCTother officessolid = grantedhover for detail · click to open
Members
6
DOCDB simple family 55312602
Offices
5
US · JP · KR
Granted
2 of 6
grant date present
Non-English titles
3
shown as filed, never translated
›IP5 & PCT — 3 members
OfficePublicationKindPublishedFiledStatusTitle
USthis patentUS-D793972-SS18 Aug 201727 Mar 2015grantedWafer carrier with a 31-pocket configuration
JPJP-1545629-SS14 Mar 201628 Sep 2015grantedno title held
KRKR-20160003441-UU6 Oct 201630 Sep 2015published31 포켓 구성을 갖는 웨이퍼 캐리어ko
›Other offices — 3 members
OfficePublicationKindPublishedFiledStatusTitle
DEDE-202015006764-U1U122 Jan 201625 Sep 2015publishedWaferträger mit einer Konfiguration mit 31 Taschende
TWTW-M531052-UU21 Oct 201625 Sep 2015published具有31個容置區的排列組態之晶圓載具zh
TWTW-D181303-SS11 Feb 201725 Sep 2015publishedWafer carrier

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Citations

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