USPatentGranted
S1

Substrate for an electronic circuit

Granted 26 May 2015 · 2 office actions

Current assignee: Kioxia Corporation · originally Toshiba

Law firm: Law firm · Log in to unlock

Attorney: Attorney · Log in to unlock

Inventors: Manabu Matsumoto, Isao Ozawa · Examiner: Elizabeth J Oswecki · AU 2912 · TC 2900

Application
29/500,867
filed 29 Aug 2014
Publication
Not published
not published
Patent· this page
US D730304
granted 26 May 2015

Life of the patent

9 dated events
⤢ drag to zoom20142016201820202022202420262028203020322034ProsecutionOwnershipTerm & fees
ProsecutionOwnershipTerm & feeshover for detail · click to open

Description

1 parts
›The patent or application file contains at least…

The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application with color drawings(s) will be provided by the Office upon request and payment of the necessary fee.

FIG. 1 is a perspective view of a substrate for an electronic circuit showing our new design;

FIG. 2 is a rear perspective view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a rear elevational view thereof;

FIG. 5 is a right side elevational view, a left side elevational view being a mirror image thereof;

FIG. 6 is a top plan view thereof; and,

FIG. 7 is a bottom plan view thereof.

The black circles shown in FIGS. 2 and 4 are flat on the surface of the electronic circuit.

The even dashed broken lines shown in the drawings represent portions of the substrate for an electronic circuit that form no part of the claimed design. The dashed-dot-dashed broken lines define the boundaries of the claimed design.

the grant prints no section headings; every part label below is ours, taken from that part's own first words

Claims

1 · 1 independent · depth 1
1 granted claims

Classifications

1 codes
USPC · US Patent Classification
D13/182

Claim changes

Soon
Coming soonHow the claims changed between publication and grant

See which claims were amended, added or cancelled during examination, with every added and removed word marked.

AmendedAddedCancelledUnchanged

The published claims of this patent are not paired with the granted ones in what we hold.

File wrapper

⤢ drag to zoomJulAugSepOctNovDec2015FebMarAprMayJunJulUSPTOApplicantNon-final rejectionResponse after non-finalNotice of allowance
USPTOApplicanthover for detail · click to open
Pendency
0.7 y
270 days filing → grant
Office actions
1
non-final + final
Responses
2
no RCE
Examiner
Elizabeth J Oswecki
art unit 2912 · TC 2900
Citations: 19 back · 0 forward

See the full prosecution history — every USPTO and applicant action on this file, in order.

Log in to unlock

Chain of title

⤢ drag to zoom20142016201820202022202420262028203020322034Owner 1Owner 3
Titlehover for detail · click to open

See the full assignment history — every owner this patent has passed through, with recordation dates and reel/frame numbers.

Log in to unlock

Term & fees

See the term timeline — pendency span, in-force span, the maintenance fees paid and both computed expiry dates.

Log in to unlock

Worldwide family

2 members · 2 offices
US1JP1
this patentIP5 & PCTother officessolid = grantedhover for detail · click to open
Members
2
DOCDB simple family 53176777
Offices
2
US · JP
Granted
2 of 2
grant date present
›IP5 & PCT — 2 members
OfficePublicationKindPublishedFiledStatusTitle
USthis patentUS-D730304-SS126 May 201529 Aug 2014grantedSubstrate for an electronic circuit
JPJP-1519750-SS23 Mar 201515 May 2014grantedno title held

Validity challenges

See the validity challenges on record — reexaminations, IPRs and PGRs, with their institution decisions and outcomes.

Log in to unlock

Citations

See every patent this one cites and every patent that cites it back — publication, assignee, and how each one was found.

Log in to unlock