Redundant power supply circuit, power over Ethernet system, and method

1. Technical Field

The disclosure relates to redundant power supply circuits, and particularly to a redundant power supply circuit used in a power over Ethernet (POE) system and method.

2. Description of Related Art

When a network device experiences power outages, the network device needs a redundant power module to supply electric signals to avoid data loss. Currently, input voltage signals of the redundant power module are transmitted from an external alternating current (AC) power system. Thus, one type of redundant power module corresponds to one type of network device, and different types of network devices need different types of redundant power modules. Therefore, there is a need for a redundant power supply circuit that can overcome the described limitations.

Many aspects of the present embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, all the views are schematic, and like reference numerals designate corresponding parts throughout the views.

FIG. 1 is a schematic diagram of a first embodiment of a POE system. The POE system comprises a redundant power supply circuit.

FIG. 2 is a schematic diagram of a second embodiment of a POE system.

FIG. 3 is a schematic diagram of a third embodiment of a POE system.

FIG. 4 is a schematic diagram of a fourth embodiment of a POE system.

FIG. 5 is a schematic diagram of a fifth embodiment of a POE system.

FIG. 6 is a schematic diagram of a sixth embodiment of a POE system.

FIG. 7 is a schematic diagram of a seventh embodiment of a POE system.

FIG. 8 is a schematic diagram of a eighth embodiment of a POE system.

FIG. 9 is a schematic diagram of a ninth embodiment of a POE system.

FIG. 10 is a flowchart of a first embodiment of a POE control method.

FIG. 11 is a flowchart of a second embodiment of a POE control method.

FIG. 12 is a flowchart of a third embodiment of a POE control method.

FIG. 13 is a flowchart of a fourth embodiment of a POE control method.

The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references can mean “at least one.”

FIG. 1 is a schematic diagram of a first embodiment of a POE system 1 . In one embodiment, the POE system 1 comprises a plurality of POE ports, such as a POE port 10 a , a POE port 10 b , a POE port 10 c , and a POE port 10 d , a redundant power supply circuit 20 , and a network device 30 . The redundant power supply circuit 20 drives the network device 30 with the POE ports 10 a , 10 b , 10 c , 10 d in parallel.

In one embodiment, the POE ports 10 a , 10 b , 10 c , 10 d are connected to the network device 30 in parallel, and the POE ports 10 a , 10 b , 10 c , 10 d are connected to a power sourcing equipment (PSE) to gain power signals via a plurality of RJ45 cables. In other embodiments, the POE ports 10 a , 10 b , 10 c , 10 d can be set in the PSE, and the POE ports 10 a , 10 b , 10 c , 10 d and the redundant power supply circuit 20 can also be set in the network device 30 .

FIG. 2 is a schematic diagram of a second embodiment of a POE system 1 a . The POE system 1 a comprises the plurality of POE ports 10 a , 10 b , 10 c , 10 d , a redundant power supply circuit 20 a , and the network device 30 . The redundant power supply circuit 20 a comprises a port detection circuit 200 , a fixed state detection circuit 202 , a voltage conversion circuit 204 , and a control circuit 206 . The port detection circuit 200 is connected to the POE ports 10 a , 10 b , 10 c , 10 d . The port detection circuit 200 detects and outputs a plurality of ready signals according to the plurality of power signals of the POE ports 10 a , 10 b , 10 c , 10 d , and each of the ready signals correspond to each of the power signals output by each of the POE ports 10 a , 10 b , 10 c , 10 d . The fixed state detection circuit 202 is connected to the network device 30 , and outputs first control signals according to a predetermined voltage signal of the network device 30 . The voltage conversion circuit 204 is connected between the POE ports 10 a , 10 b , 10 c , 10 d and the network device 30 , and converts the plurality of power signals of the POE ports 10 a , 10 b , 10 c , 10 d to driving voltage signals to drive the network device 30 . The control circuit 206 receives the first control signals from the fixed state detection circuit 202 and the plurality of ready signals from the port detection circuit 200 , and generates and sends enable signals to the voltage conversion circuit 204 according to the first control signals and the plurality of ready signals.

In one embodiment, the voltage conversion circuit 204 further determines if the voltage conversion circuit 204 receives the enable signals to convert the plurality of power signals. When the voltage conversion circuit 204 receives the enable signals, the voltage conversion circuit 204 converts the plurality of power signals output by the POE ports 10 a , 10 b , 10 c , 10 d to the driving voltage signals to drive the network device 30 . When the voltage conversion circuit 204 does not receive the enable signals, the voltage conversion circuit 204 suspends converting, and a value of the driving voltage signals is 0 V.

In one embodiment, when the POE port 10 a outputs the power signals, the port detection circuit 200 outputs the ready signals corresponding to the power signals output by the POE port 10 a . When the POE port 10 a does not output the power signals, the port detection circuit 200 has no corresponding ready signals to output.

FIG. 3 is a schematic diagram of a third embodiment of a POE system 1 b . In the embodiment, the POE system 1 b comprises the plurality of POE ports 10 a , 10 b , 10 c , 10 d , a redundant power supply circuit 20 b , and the network device 30 . The redundant power supply circuit 20 b is similar to the redundant power supply circuit 20 a of the second embodiment. The difference between the redundant power supply circuit 20 a and the redundant power supply circuit 20 b is that the redundant power supply circuit 20 b further comprises a sampling circuit 208 and a first dynamic state detection circuit 210 .

The sampling circuit 208 is connected to the voltage conversion circuit 204 , and samples current signals flowing through the voltage conversion circuit 204 to output first sampling voltage signals. The first dynamic state detection circuit 210 is connected to the sampling circuit 208 , the control circuit 206 , and the POE ports 10 a , 10 b , 10 c , 10 d , and outputs second control signals according to the first sampling voltage signals output by the sampling circuit 208 . The control circuit 206 further generates the enable signals according to the second control signals and the plurality of ready signals. The voltage conversion circuit 204 determines whether the plurality of power signals are converted into the driving voltage signals according to whether the voltage conversion circuit 204 receives the enable signal from the control circuit 206 , and the POE ports 10 a , 10 b , 10 c , 10 d further determines if the POE ports 10 a , 10 b , 10 c , 10 d suspend work according to the second control signals. When the POE ports 10 a , 10 b , 10 c , 10 d receive the second control signals, the POE ports 10 a , 10 b , 10 c , 10 d suspend work. When the POE ports 10 a , 10 b , 10 c , 10 d do not receive the second control signals, the POE ports 10 a , 10 b , 10 c , 10 d are in a working state for outputting the power signals.

In one embodiment, the power signals of the network device 30 is supplied by the voltage conversion circuit 204 so that the sampling circuit 208 can be connected to the voltage conversion circuit 204 to sample the current signals, or can be connected to the network device 30 to sample the current signals.

In one embodiment, when the network device 30 is in a full load state, the network device 30 has a maximum power need. The current signals sampled by the sampling circuit 208 are in the full load state flowing through the network device 30 , and the POE ports 10 a , 10 b , 10 c , 10 d determine the number of the POE ports 10 a , 10 b , 10 c , 10 d needed to drive the network device 30 according to the maximum power of the network device 30 . Thereby, the power of the power signals supplied by the redundant power supply circuit 20 b is substantially matched with the power needed by the network device 30 in the working state.

FIG. 4 is a schematic diagram of a fourth embodiment of a POE system 1 c . In the embodiment, the fixed state detection circuit 202 comprises a first comparison circuit 2022 and a first isolation circuit 2024 . The first comparison circuit 2022 compares the predetermined voltage signal of the network device 30 with a plurality of reference voltage signals (such as a reference voltage signal Vref 1 , a reference voltage signal Vref 2 , and a reference voltage signal Vref 3 ) to output the first control signals. The first comparison circuit 2022 comprises a plurality of first comparison units 2022 a , 2022 b , 2022 c . Each of the first comparison units 2022 a , 2022 b , 2022 c compares the predetermined voltage signal with each of the reference voltage signals Vref 1 , Vref 2 , Vref 3 . That is, the first control signals output by the fixed state detection circuit 202 comprises a plurality of comparison signals output by the first comparison units 2022 a , 2022 b , 2022 c . A first terminal of the first isolation circuit 2024 is connected to the first comparison circuit 2022 , and a second terminal of the first isolation circuit 2024 is connected to a node between the port detection circuit 200 and the control circuit 206 . The first isolation circuit 2024 isolates the first comparison circuit 202 from the port detection circuit 200 so that the port detection circuit 200 can transmit the plurality of ready signals to the control circuit 206 . The first isolation circuit 2024 comprises a plurality of first isolation units 2024 a , 2024 b , 2024 c . Each of the first isolation units 2024 a , 2024 b , 2024 c isolates each of the first comparison units 2022 a , 2022 b , 2022 c from the port detection circuit 200 .

In one embodiment, the predetermined voltage signal is determined by a theoretical power of the network device 30 . The theoretical power is a maximum value that all modules of the network device 30 are in the working state.

In one embodiment, the plurality of POE ports are four POE ports 10 a , 10 b , 10 c , 10 d . Three first comparison units 2022 a , 2022 b , 2022 c can output four types first control signals corresponding to four power levels so that the number of the plurality of first comparison units is three, the number of the plurality of reference voltage signals is three, and the number of the plurality of first isolation units is three. Each of the first isolation units 2024 a , 2024 b , 2024 c is connected to each of the comparison units 2022 a , 2022 b , 2022 c , respectively. The number of the plurality of first comparison units is equivalent to the number of the plurality of first isolation units. In other embodiments, when the number of the plurality of POE ports is N(N=1, 2, 3, 4 . . . ), the number of the plurality of first comparison units and the number of the plurality of first isolation units both are N−1. That is, the number of the plurality of first comparison units is one less than the number of the plurality of POE ports.

The first dynamic state detection circuit 210 comprises an amplification circuit 2100 , a second comparison circuit 2102 , a temporary signal storage circuit 2104 , a second isolation circuit 2106 , and a switch circuit 2108 . The amplification circuit 2100 amplifies the first sampling voltage signals output by the sampling circuit 208 into second sampling voltage signals. The second comparison circuit 2102 comprises a plurality of comparison units 2102 a , 2102 b , 2102 c , and compares the second sampling voltage signals with the plurality of reference voltage signals to output the second control signals. The temporary signal storage circuit 2104 comprises a plurality of temporary signal storage units 2104 a , 2104 b , 2104 c , and receives and stores the second control signals. A first terminal of the second isolation circuit 2106 is connected to the temporary signal storage circuit 2104 , and a second terminal of the second isolation circuit 2106 is connected to a node between the port detection circuit 200 and the control circuit 206 . The second isolation circuit 2106 comprises a plurality of second isolation units 2106 a , 2106 b , 2106 c , and isolates the temporary signal storage circuit 2104 from the port detection circuit 200 so that the port detection circuit 200 can transmit the plurality of ready signals to the control circuit 206 . The switch circuit 2108 comprises a plurality of switch units 2108 a , 2108 b , 2108 c . The switch circuit 2108 is connected to the temporary signal storage circuit 2104 , and outputs a plurality of suspending signals according to the second control signals output by the temporary signal storage circuit 2104 . The POE ports 10 a , 10 b , 10 c , 10 d further determine if the POE ports 10 a , 10 b , 10 c , 10 d suspend work according to the plurality of suspending signals output by the switch units 2108 a , 2108 b , 2108 c.

In one embodiment, the plurality of POE ports are four POE ports 10 a , 10 b , 10 c , 10 d , and the first sampling voltage signals are signals that are output by the sampling circuit 208 when the network device 30 is in the full load state. The first dynamic state detection circuit 210 determines the number of the POE ports 10 a , 10 b , 10 c , 10 d needed by the network device 30 according to the second control signals. To ensure the network device 30 is in the working state, one or more POE ports 10 a , 10 b , 10 c , 10 d should output the power signals. Therefore, the first dynamic state detection circuit 210 can turn off three POE ports 10 b , 10 c , 10 d at most so that the number of the plurality of second comparison units is three, the number of the plurality of reference voltage signals is three, the number of the plurality of temporary signal storage units is three, the number of the plurality of second isolation units is three, and the number of the plurality of switch units is three. In other embodiments, when the number of the plurality of POE ports is N (N=1, 2, 3, 4 . . . ), the number of the plurality of second comparison units, the number of the plurality of temporary signal storage unit, the number of the plurality of second isolation units, and the number of the plurality of switch units are all N−1.

FIG. 5 is a circuit diagram of a fifth embodiment of a POE system 1 d . In the embodiment, the plurality of POE ports comprise four POE ports 10 a , 10 b , 10 c , 10 d . The port detection circuit 200 comprises a first detection terminal, a second detection terminal, a third detection terminal, a fourth detection terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal. The port detection circuit 200 determines if the POE ports 10 a , 10 b , 10 c , 10 d output power signals via the first detection terminal, the second detection terminal, the third detection terminal, and the fourth detection terminal, and respectively outputs the plurality of ready signals via the first signal output terminal, the second signal output terminal, the third signal output terminal, and the fourth signal output terminal after detecting the POE ports 10 a , 10 b , 10 c , 10 d are outputting the power signals. In one embodiment, when the port detection circuit 200 detects that the POE port 10 a outputs the power signals, the first signal output terminal of the port detection circuit 200 outputs the ready signals corresponding to the POE port 10 a . When the port detection circuit 200 detects that the POE port 10 b outputs the power signals, the second signal output terminal of the port detection circuit 200 outputs the ready signals corresponding to the POE port 10 b . When the port detection circuit 200 detects that the POE port 10 c outputs the power signals, the third signal output terminal of the port detection circuit 200 outputs the ready signals corresponding to the POE port 10 c . When the port detection circuit 200 detects that the POE port 10 d outputs the power signals, the fourth signal output terminal of the port detection circuit 200 outputs the ready signals corresponding to the POE port 10 d.

In one embodiment, the port detection circuit 200 can be a known port detection module that detects the power signals of the POE ports 10 a , 10 b , 10 c , 10 d , i.e., port detection modules that already exist in current technology.

The first comparison unit 2022 a comprises a first comparator C 11 , the first comparison unit 2022 b comprises a first comparator C 12 , and the first comparison unit 2022 c comprises a first comparator C 13 . The first isolation unit 2024 a comprises a first diode D 11 , the first isolation unit 2024 b comprises a first diode D 12 , and the first isolation unit 2024 c comprises a first diode D 13 . The first comparator C 11 comprises a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the first comparator C 11 receives the reference voltage signal Vref 1 , the negative input terminal of the first comparator C 11 is connected to the network device 30 , to receive the predetermined voltage signal from the network device 30 , the output terminal of the first comparator C 11 is connected to an anode of the first diode D 11 , and a cathode of the first diode D 11 is connected to a first node between the port detection circuit 200 and the control circuit 206 . The first comparator C 12 comprises a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the first comparator C 12 receives the reference voltage signal Vref 2 , the negative input terminal of the first comparator C 12 is connected to the network device 30 , to receive the predetermined voltage signal from the network device 30 , the output terminal of the first comparator C 12 is connected to an anode of the first diode D 12 , and a cathode of the first diode D 12 is connected to a second node between the port detection circuit 200 and the control circuit 206 . The first comparator C 13 comprises a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the first comparator C 13 receives the reference voltage signal Vref 3 , the negative input terminal of the first comparator C 13 is connected to the network device 30 , to receive the predetermined voltage signal from the network device 30 , the output terminal of the first comparator C 13 is connected to an anode of the first diode D 13 , and a cathode of the first diode D 13 is connected to a third node between the port detection circuit 200 and the control circuit 206 . The first comparison units 2022 a , 2022 b , 2022 c can be other voltage comparison modules, and the first isolation units 2024 a , 2024 b , 2024 c can also be other signal isolation modules in other embodiments.

In one embodiment, a value of the reference voltage signal Vref 3 is greater than a value of the reference voltage signal Vref 2 , and the value of the reference voltage signal Vref 2 is greater than a value of the reference voltage signal Vref 1 . The first comparator C 11 , C 12 , C 13 respectively compares the reference voltage signals Vref 1 , Vref 2 , Vref 3 with the predetermined voltage signal of the network device 30 to output the plurality of comparison signals, to make a fixed state detection circuit 202 a output the first control signals according to the predetermined voltage signal of the network device 30 .

In one embodiment, in response to the POE ports 10 a , 10 b , 10 c , 10 d operating according to the IEEE802.3 standard, each of the POE ports 10 a , 10 b , 10 c , 10 d can supply 25 W (watt) power at most. Therefore, four POE ports 10 a , 10 b , 10 c , 10 d can supply 100 W power at most, and the value of the theoretical power of the network device 30 should be less than 100 W. The plurality of power signals output by the POE ports 10 a , 10 b , 10 c , 10 d can be partitioned into four power levels, such as a first power level 0-25 W, a second power level 25-50 W, a third power level 50-75 W, and a fourth power level 75-100 W.

In one embodiment, the larger the value of the theoretical power, the larger the value of the predetermined voltage signal. When a value of the theoretical power is 0-25 W, a value of the predetermined voltage signal is 0-1.25V. When the value of the theoretical power is 25-50 W, the value of the predetermined voltage signal is 1.25-2.5V. When the value of the theoretical power is 50-75 W, the value of the predetermined voltage signal is 2.5-3.75V. When the value of the theoretical power is 75-100 W, the value of the predetermined voltage signal is 3.75-5V. Three reference voltage signal Vref 1 , Vref 2 , Vref 3 can determine four power levels so that the reference voltage signal Vref 1 is 1.25V, the reference voltage signal Vref 2 is 2.5V, and the reference voltage signal Vref 3 is 3.75V. Each of the reference voltage signals is corresponding to each of the power levels of the plurality of power signals. In other embodiments, when the value of the theoretical power of the network device 30 is greater than 100 W, the fixed state detection circuit 202 a can add a first comparator, a first diode, and a reference voltage signal in at per 25 W to meet the actual circuit design.

The voltage conversion circuit 204 can be a known power modules that convert the plurality of power signals, i.e., power modules that already exist in current technology.

The control circuit 206 comprises a plurality of AND gatesAN 1 , AN 2 , AN 3 . In one embodiment, each of the AND gates AN 1 , AN 2 , AN 3 comprises two input terminals, and the number of the POE ports 10 a , 10 b , 10 c , 10 d is four so that the number of the AND gates AN 1 , AN 2 , AN 3 is three. The AND gate AN 1 comprises a first input terminal, a second input terminal, and a output terminal. The first input terminal of the AND gate AN 1 is connected to the first signal output terminal of the port detection circuit 200 , and the second input terminal of the AND gate AN 1 is connected to the cathode of the first diode D 11 and the second output terminal of the port detection circuit 200 . The AND gate AN 2 comprises a first input terminal, a second input terminal, and an output terminal. The first input terminal of the AND gate AN 2 is connected to the cathode of the first diode D 12 and the third output terminal of the port detection circuit 200 , and the second input terminal of the AND gate AN 2 is connected to the cathode of the first diode D 13 and the fourth output terminal of the port detection circuit 200 . The AND gate AN 3 comprises a first input terminal, a second input terminal, and a output terminal. The first input terminal of the AND gate AN 3 is connected to the output terminal of the AND gate AN 1 , the second input terminal of the AND gate AN 3 is connected to the output terminal of the AND gate AN 2 , and the output terminal of the AND gate AN 3 is connected to the voltage conversion circuit 204 .

In one embodiment, when the two input terminals of the AND gates AN 1 , AN 2 are both in a high level (logic 1), the output terminal of the AND gate AN 3 is at the high level, and the control circuit 206 outputs the enable signals. That is, the AND gates AN 1 , AN 2 , AN 3 output the enable signals when a value of power supplied by the POE ports 10 a , 10 b , 10 c , 10 d is greater than the value of the theoretical power of the network device 30 . In other embodiments, the control circuit 206 can be other modules or chips that output the enable signals, i.e., Micro Controller Unit (MCU), Single Chip Micyoco (SCM) that already exist in current technology.

In one embodiment, when the value of the theoretical power of the network device 30 is 60 W, the POE system 1 d needs three POE ports 10 a , 10 b , 10 c because each of the POE ports 10 a , 10 b , 10 c can supply 25 W power at most, and the value of the predetermined voltage signal of the network device 30 is less than 3.75V and greater than 2.5V. The reference voltage signal Vref 1 is 1.25V, the reference voltage signal Vref 2 is 2.5V, and the reference voltage signal Vref 3 is 3.75V so that the first comparator C 11 , C 12 both output a low level signal, and the first comparator C 13 outputs a high level signal. When the first detection terminal, the second detection terminal, and the third detection terminal of the port detection circuit 200 respectively detects that the POE ports 10 a , 10 b , 10 c output the power signals, the first signal output terminal, the second signal output terminal, and the third signal output terminal of the port detection circuit 200 output the high level. Whether the POE ports 10 d output the power signals or not, the two input terminals of the AND gate AN 1 , AN 2 are both at the high level because of isolation functions of the first diode D 11 , D 12 , D 13 . The output terminal of the AND gate AN 3 is at the high level so that the control circuit 206 outputs the enable signals and sends the enable signals to the voltage conversion circuit 204 , and the voltage conversion circuit 204 converts the power signals to drive the network device 30 . When the port detection circuit only detects that two POE ports 10 a , 10 b output the power signals, the third signal output terminal of the port detection circuit 200 is at the low level (logic 0), the output terminal of the first comparator C 12 is at the low level so that the first input terminal of the AND gate AN 2 is at the low level, the output terminal of the AND gate AN 3 is at the low level, the control circuit 206 has no enable signals to output, the voltage conversion circuit 204 suspends converting, and the value of the driving voltage signals is 0V. When the voltage conversion circuit 204 is in the working state, the control circuit 206 ensures that the value of the power supplied by the POE ports 10 a , 10 b , 10 c , 10 d is greater than the value of the theoretical power of the network device 30 , to avoid the power supplied by the POE ports 10 a , 10 b , 10 c , 10 d failing to meet a requirement of the network device 30 and damaging the network device 30 .

When the port detection circuit 200 detects that no less than three POE ports 10 a , 10 b , 10 c output the power signals, the control circuit 206 outputs the enable signals, and the voltage conversion circuit 204 converts the power signals to drive the network device 30 . In other embodiments, the theoretical power of the network device 30 is 80 W. When the port detection circuit 200 detects that no less than four POE ports 10 a , 10 b , 10 c , 10 d outputs the power signals, the control circuit 206 outputs the enable signals, and the voltage conversion circuit 204 converts the power signals to drive the network device 30 .

The sampling circuit 208 comprises a resistor Rs, a first end of the resistor Rs is connected to the voltage conversion circuit 204 , and a second end of the resistor Rs is grounded. The resistor Rs samples and converts the current signals flowing through the voltage conversion circuit 204 into the first sampling voltage signals.

In one embodiment, a resistance of the resistor Rs is determined by actual circuit designs. The sampling circuit 208 can include a current transformer instead of the resistor Rs to sample the current signals, and the sampling circuit 208 can be other sampling modules in other embodiments.

The amplification circuit 2100 comprises an amplifier A 1 . The second comparison unit 2102 a comprises a second comparator C 21 , the second comparison unit 2102 b comprises a second comparator C 22 , and the second comparison unit 2102 c comprises a second comparator C 23 . The temporary signal storage unit 2104 a comprises an OR gate OR 1 , the temporary signal storage unit 2104 b comprises an OR gate OR 2 , and the temporary signal storage unit 2104 c comprises an OR gate OR 3 . The second isolation unit 2106 a comprises a second diode D 21 , the second isolation unit 2106 b comprises a second diode D 22 , and the second isolation unit 2106 c comprises a second diode D 23 . The switch unit 2108 a comprises a switch Q 1 , the switch unit 2108 b comprises a switch Q 2 , and the switch unit 2108 c comprises a switch Q 3 . The amplifier A 1 comprises a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the amplifier A 1 is connected to a node between the resistor Rs and the voltage conversion circuit 204 , the negative input terminal of the amplifier A 1 is grounded, and the amplifier A 1 amplifies the first sampling voltage signals into the second sampling voltage signals. The second comparator C 21 comprises a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the second comparator C 21 receives the reference voltage signal Vref 1 , and the negative input terminal of the second comparator C 21 is connected to the output terminal of the amplifier A 1 . The second comparator C 22 comprises a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the second comparator C 22 receives the reference voltage signal Vref 2 , and the negative input terminal of the second comparator C 22 is connected to the output terminal of the amplifier A 1 . The second comparator C 23 comprises a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the second comparator C 23 receives the reference voltage signal Vref 3 , and the negative input terminal of the second comparator C 23 is connected to the output terminal of the amplifier A 1 . The OR gate OR 1 comprises a first input terminal, a second input terminal, and an output terminal. The first input terminal of the OR gate OR 1 is connected to the output terminal of the second comparator C 21 , the output terminal of the OR gate OR 1 is connected to an anode of the second diode D 21 , the second input terminal of the OR gate OR 1 is connected to a node between the second diode D 21 and the output terminal of the OR gate OR 1 , and an cathode of the second diode D 21 is connected to a node between the first diode D 11 and the port detection circuit 200 . The OR gate OR 2 comprises a first input terminal, a second input terminal, and an output terminal. The first input terminal of the OR gate OR 2 is connected to the output terminal of the second comparator C 22 , the output terminal of the OR gate OR 2 is connected to an anode of the second diode D 22 , the second input terminal of the OR gate OR 2 is connected to a node between the second diode D 22 and the output terminal of the OR gate OR 2 , and an cathode of the second diode D 22 is connected to a node between the first diode D 12 and the port detection circuit 200 . The OR gate OR 3 comprises a first input terminal, a second input terminal, and an output terminal. The first input terminal of the OR gate OR 3 is connected to the output terminal of the second comparator C 23 , the output terminal of the OR gate OR 3 is connected to an anode of the second diode D 23 , the second input terminal of the OR gate OR 3 is connected to a node between the second diode D 23 and the output terminal of the OR gate OR 3 , and an cathode of the second diode D 23 is connected to a node between the first diode D 13 and the port detection circuit 200 . The switch Q 1 comprises a first terminal, a second terminal, and a control terminal. The first terminal of the switch Q 1 is connected to the POE port 10 b , the second terminal of the switch Q 1 is grounded, and the control terminal of the switch Q 1 is connected to a node between the OR gate OR 1 and the second diode D 21 . The switch Q 2 comprises a first terminal, a second terminal, and a control terminal. The first terminal of the switch Q 2 is connected to the POE port 10 c , the second terminal of the switch Q 2 is grounded, and the control terminal of the switch Q 2 is connected to a node between the OR gate OR 2 and the second diode D 22 . The switch Q 3 comprises a first terminal, a second terminal, and a control terminal. The first terminal of the switch Q 3 is connected to the POE port 10 d , the second terminal of the switch Q 3 is grounded, and the control terminal of the switch Q 3 is connected to a node between the OR gate OR 3 and the second diode D 23 .

In one embodiment, the second control signals comprise a plurality of comparison signals output by the second comparators C 21 , C 22 , C 23 .

When the first dynamic state detection circuit 210 is in the working state, the redundant power supply circuit 20 d controls the network device 30 in the full load state for a brief time to make the current signals flowing through the voltage conversion circuit 204 have a maximum value. The first dynamic state detection circuit 210 outputs the second control signals according to the first sampling voltage signals output by the sampling circuit 208 in the full load state, and controls the POE ports 10 a , 10 b , 10 c , 10 d turned off according to the maximum power needed by the network device 30 . The first dynamic state detection circuit 210 precisely determines the number of POE ports 10 a , 10 b , 10 c , 10 d needed by the network device 30 in a working state, to avoid a maximum difference between the value of the theoretical power and the value of the maximum power of the network device 30 that cause unnecessary power signals supplied by the POE ports.

In one embodiment, the value of the theoretical power of the network device 30 is 60 W, the value of the maximum power of the network device 30 is 40 W, and each of the POE ports supply 25 W power. In an initial state, the port detection circuit 202 a must detect three POE ports 10 a , 10 b , 10 c outputting power signals, to control the control circuit 206 to output the enable signals, and the voltage conversion circuit 204 converts the power signals according to the enable signals to drive the network device 30 . The first terminal of the switches Q 1 , Q 2 , Q 3 are high level. In a stable state, the network device 30 only needs two POE ports 10 a , 10 b to drive so that the first dynamic state detection circuit 210 should turn off the POE port 10 c . In the initial state, the fixed state detection circuit 202 a outputs the first control signals, and the first terminal of the switches Q 1 , Q 2 , Q 3 are high level. In the stable state, the fixed state detection circuit 202 a suspends outputting the first control signals, the first dynamic state detection circuit 210 detects that the value of the maximum power of the network device 30 is 40 W so that the value of the second sampling voltage signals output by the amplifier A 1 is greater than 1.25V and less than 2.5V. The output terminal of the second comparator C 21 is at the low level, the output terminal of the OR gate OR 1 is at the low level, the output terminal of the second comparators C 22 , C 23 are at the high level, and the output terminal of the OR gates OR 2 , OR 3 are at the high level. The output terminal of the OR gates OR 1 , OR 2 , OR 3 keep the electrical level state until the redundant power supply circuit 20 d resets.

When the port detection circuit 200 detects the POE ports 10 a , 10 b output the power signals, the output terminal of the AND gate AN 1 is at a high level. Whether the POE ports 10 c , 10 d output the power signals or not, the output terminal of the AND gate AN 2 is at a high level, and the control circuit 206 outputs and sends the enable signals to the voltage conversion circuit 204 driving the network device 30 . When the POE ports 10 a , 10 b both output the power signals, the control circuit 206 continues outputting and sending the enable signals to the voltage conversion circuit 204 because the OR gates OR 1 , OR 2 , OR 3 stay in the electrical level state.

In the stable state, the switch Q 1 is turned off, the first terminal of the switch Q 1 is high level, the switches Q 2 , Q 3 are turned on, and the first terminal of the switches Q 2 , Q 3 both change to low level. The switch circuit 2108 outputs and sends the suspending signals to the POE ports 10 c , 10 d according to the electrical level changes of the switches Q 2 , Q 3 . The POE ports 10 c , 10 d are turned off or remain turned off after receiving the suspending signals, and the POE ports 10 c , 10 d have no power signals to output.

In one embodiment, an amplification factor of the amplifier A 1 is determined by actual circuit designs. The switches Q 1 , Q 2 , Q 3 can be an N type metal-oxide semiconductor field effect transistor (NMOSFET), a P type metal-oxide semiconductor field effect transistor (PMOSFET), a npn type transistor, and a pnp type transistor. In other embodiments, the amplification circuit 2100 can be a transistor to amplify the first sampling voltage signals, or other amplification modules. The temporary signal storage units 2104 a , 2104 b , 2104 c can be a flip-flop, or other storage modules. The second comparison units 2102 a , 2102 b , 2102 c can be other voltage comparison modules, and the second isolation units 2104 a , 2104 b , 2104 c can be other signal isolation modules.

In one embodiment, a needed power of network device 30 is greater than 0 W in the working state so that three POE ports 10 b , 10 c , 10 d are turned off at most according to the second control signals output by the first dynamic state detection circuit 210 , the number of the second comparators C 21 , C 22 , C 23 is three, the number of the OR gates OR 1 , OR 2 , OR 3 is three, the number of the second diodes D 21 , D 22 , D 23 is three, and the number of the switches Q 1 , Q 2 , Q 3 is three. In other embodiments, when the number of POE ports is greater than four, the first dynamic state detection circuit 210 can add a second comparator, an OR gate, a second diode, a switch, and a reference voltage signal in per POE port.

FIG. 6 is a schematic diagram of a sixth embodiment of a POE system 1 e . In the embodiment, the POE system 1 e comprises the plurality of POE ports 10 a , 10 b , 10 c , 10 d , a redundant power supply circuit 20 e , and the network device 30 . The redundant power supply circuit 20 e comprises the port detection circuit 200 , the fixed state detection circuit 202 , the voltage conversion circuit 204 , and a MCU U 1 . The port detection circuit 200 , the fixed state detection circuit 202 , and the voltage conversion circuit 204 are similar to the port detection circuit 200 , the fixed state detection circuit 202 , and the voltage conversion circuit 204 of the second embodiment. The MCU U 1 is connected to the port detection circuit 200 , the fixed state detection circuit 202 , and the voltage conversion circuit 204 , and generates and sends the enable signals to the voltage conversion circuit 204 according to the first control signals output by the fixed state detection circuit 202 and the plurality of ready signals output by the port detection circuit 200 .

FIG. 7 is a schematic diagram of a seventh embodiment of a POE system 1 f . In the embodiment, the POE system if comprises the plurality of POE ports 10 a , 10 b , 10 c , 10 d , a redundant power supply circuit 20 f , and the network device 30 . The redundant power supply circuit 20 f is similar to the redundant power supply circuit 20 e of the sixth embodiment. The difference between the redundant power supply circuit 20 f and the redundant power supply circuit 20 e is that the redundant power supply circuit 20 f further comprises the sampling circuit 208 and a second dynamic state detection circuit 212 .

The second dynamic state detection circuit 212 is connected to the sampling circuit 208 and the MCU U 1 , and outputs the second control signals according to the first sampling voltage signals output by the sampling circuit 208 . The MCU U 1 further generates the enable signals according to the second control signals output by the second dynamic state detection circuit 212 and the plurality of ready signals output by the port detection circuit 200 .

The MCU U 1 is further connected to the POE ports 10 a , 10 b , 10 c , 10 d , and outputs third control signals according to the second control signals output by the second dynamic state detection circuit 212 . The POE ports 10 a , 10 b , 10 c , 10 d further determine if the POE ports 10 a , 10 b , 10 c , 10 d suspend work according to the third control signals. When the POE ports 10 a , 10 b , 10 c , 10 d receive the third control signals, the POE ports 10 a , 10 b , 10 c , 10 d suspend outputting the power signals.

FIG. 8 is a schematic diagram of an eighth embodiment of a POE system 1 g . In the embodiment, the second dynamic state detection circuit 212 comprises the amplification circuit 2100 and a AD converter U 2 . The AD converter U 2 is connected between the MCU U 1 and the amplification circuit 2100 , and outputs the second control signals to the MCU U 1 according to the second sampling voltage signals output by the amplification circuit 2100 .

FIG. 9 is a circuit diagram of a ninth embodiment of a POE system 1 h . In the embodiment, a fixed state detection circuit 202 b is similar to the fixed state detection circuit 202 a of the fifth embodiment. The difference between the fixed state detection circuit 202 b and the fixed state detection circuit 202 a is that the fixed state detection circuit 202 b only comprises the first comparators C 11 , C 12 , C 13 and the reference voltage signals Vref 1 , Vref 2 , Vref 3 . The output terminals of the first comparators C 11 , C 12 , C 13 are connected to the MCU U 1 , and the fixed state detection circuit 202 b outputs the first control signals according to the comparison signals output by the first comparators C 11 , C 12 , C 13 . The AD converter U 2 converts the second sampling voltage signals output by the amplifier A 1 into the second control signals, and sends to the MCU U 1 . The MCU U 1 gains the maximum power of the network device 30 according to the second control signals, and outputs the third control signals to control a part of POE ports to turn off to avoid unnecessary power signals being supplied by POE ports.

FIG. 10 is a flowchart of a first embodiment of a POE control method. In block S 1000 , the port detection circuit 200 detects and outputs the plurality of ready signals according to the plurality of power signals of the POE ports 10 a , 10 b , 10 c , 10 d . In block S 1002 , the fixed state detection circuit 202 outputs the first control signals according to the predetermined voltage signal of the network device 30 . In block S 1004 , the control circuit 206 generates and sends the enable signals to the voltage conversion circuit 204 according to the first control signals and the plurality of ready signals. In block S 1006 , the voltage conversion circuit 204 converts the plurality of power signals according to whether the voltage conversion circuit 204 receives the enable signal from the control circuit 206 .I In response to the voltage conversion circuit 204 receiving the enable signals, the voltage conversion circuit converts the plurality of power signals, and in response to the voltage conversion circuit 204 not receiving the enable signals, the voltage conversion circuit 204 suspends converting.

FIG. 11 is a flowchart of a second embodiment of a POE control method. In the embodiment, blocks S 1100 , S 1102 , S 1104 , S 1112 are similar to blocks S 1000 , S 1002 , S 1004 , S 1006 of the first embodiment, correspondingly. In block S 1106 , the first dynamic state detection circuit 210 outputs the second control signals according to the first sampling voltage signals output by the sampling circuit 208 . In block S 1108 , the control circuit 206 further generates the enable signals according to the second control signals output by the first dynamic state detection circuit 210 and the plurality of ready signals output by the port detection circuit 200 . In block S 1110 , the POE ports 10 a , 10 b , 10 c , 10 d determines if the POE ports 10 a , 10 b , 10 c , 10 d suspends work according to the second control signals output by the first dynamic state detection circuit 210 .

FIG. 12 is a flowchart of a third embodiment of a POE control method. In the embodiment, blocks S 1200 , S 1202 , S 1206 are similar to blocks S 1000 , S 1002 , S 1006 of the first embodiment, respectively. In block S 1204 , the MCU U 1 generates the enable signals according to the first control signals and the plurality of ready signals.

FIG. 13 is a flowchart of a fourth embodiment of a POE control method. In the embodiment, blocks S 1300 , S 1302 , S 1314 are similar to blocks S 1000 , S 1002 , S 1006 of the first embodiment, respectively, and block S 1304 is similar to block S 1204 of the third embodiment. In block S 1306 , the second dynamic state detection circuit 212 outputs the second control signals according to the first sampling voltage signals output by the sampling circuit 208 . In block S 1308 , the MCU U 1 further generates the enable signals according to the second control signals output by the second dynamic state detection circuit 212 and the plurality of ready signals output by the port detection circuit 200 . In block S 1310 , the MCU U 1 outputs the third control signals according to the second control signals output by the second dynamic state detection circuit 212 . In block S 1312 , the POE 10 a , 10 b , 10 c , 10 d ports determines if the POE ports 10 a , 10 b , 10 c , 10 d suspend work according to the third control signals.

The foregoing disclosure of various embodiments has been presented for the purposes of illustration. It is not intended to be exhaustive or limited to the precise forms disclosed. Many variations and modifications of the embodiments described herein will be apparent to one of ordinary skill in the art in the light of the above disclosure. The scope is to be defined only by the claims appended hereto and their equivalents.