Circuit and method for overcurrent detection of power switch

This application claims the benefit of priority to People's Republic of China Patent Application Serial No. 201210256237.7, filed Jul. 19, 2012.

The on and off properties of a power switch, namely, a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), is often used to implement efficient conversion of signals and energy in a switch power supply, a switch amplifier, a charge pump, and the like. Typically, a large current passes through a power MOSFET when the power MOSFET is on, and if the current passing through the power MOSFET exceeds the tolerance of the power MOSFET, the power MOSFET may be damaged permanently. Therefore, in order to ensure the reliability of the power MOSFET, continuous detection may be performed on the current passing through the power MOSFET, and overcurrent protection over the power MOSFET may be performed when the passing current is too large.

FIG. 1 gives an overcurrent detection circuit for the case in which an N-type MOSFET (NMOS) serves as the power switch. As shown in FIG. 1 , NMOS N 1 as a power switch has a ratio of N:1 in size over NMOS N 2 , and is in common-gate and common-drain connection with NMOS N 2 , with both gates connected to a first bias voltage CP 1 , and both drains connected to an input voltage Vin. The source of NMOS N 1 is connected to the negative input of an amplifier A 1 , and the source of NMOS N 2 is connected to the positive input of the amplifier A 1 and the drain of an NMOS N 3 . The output of the amplifier A 1 is connected to the gate of NMOS N 3 , which is in common-gate and common-source connection with an NMOS N 4 , with both sources connected to ground. The drain of NMOS N 4 is connected to a resistor R 1 and the negative input of a comparator OP 1 . One end of resistor R 1 is connected to the drain of NMOS N 4 , and the other end of resistor R 1 is connected to voltage Vin. One end of a resistor R 2 is connected to the positive input of comparator OP 1 and a reference current source Q 1 , and the other end of R 2 is connected to input voltage Vin. The power terminal of comparator OP 1 is connected to input voltage Vin, and comparator OP 1 generates an output signal OCP.

During the operation of the overcurrent detection circuit shown in FIG. 1 , as amplifier A 1 is in negative feedback connection, the virtual shorting effect of amplifier A 1 equalizes the voltages at the positive and negative inputs of the amplifier A 1 . NMOS N 2 samples the current passing through NMOS N 1 , which is N times of the current passing through NMOS N 2 , where N is a positive integer. The current passing through NMOS N 3 is that through NMOS N 2 . NMOS N 4 mirrors the current in NMOS N 3 , resulting in a current Is passing through NMOS N 4 . The voltage drop across resistor R 1 is R 1 *Is, the voltage drop across resistor R 2 is R 2 *Ir, where Ir indicates the current supplied by reference current source Q 1 . When the current passing through NMOS N 1 is small, the current passing through NMOS N 2 is also small and R 1 *Is<R 2 Ir. The output signal OCP of comparator OP 1 is low or inactive in this case; indicating no overcurrent in NMOS N 1 . When the current passing through NMOS N 1 reaches an overcurrent protection threshold, or R 1 *Is>R 2 Ir, the output signal OCP of comparator OP 1 is high or active; indicating that an overcurrent has occurred in NMOS N 1 .

There are some drawbacks to the circuit of FIG. 1 . In the overcurrent detection circuit shown in FIG. 1 , input voltage Vin is typically has a high voltage value, and thus each device in the circuit has to be able to tolerate higher voltages. Additionally, there will be a large error in the current Is passing through NMOS N 4 obtained by current mirroring; reducing the accuracy of overcurrent detection.

Further, the amplifier A 1 in FIG. 1 has a structure typically as shown in FIG. 2 . The gate of NMOS N 21 is the negative input, the source of NMOS N 21 is connected to the source of NMOS N 22 , and to the ground via a current source Q 21 , and the drain of NMOS N 21 is connected to the drain of and the gate of a P-type MOSFET (PMOS) P 21 , and to the gate of PMOS P 22 . PMOS P 21 and PMOS P 22 are in common-source and common-gate connection, forming a current mirroring circuit. The gate of NMOS N 22 is the positive input of the amplifier, the drain of NMOS N 22 is connected to that of PMOS P 22 and the gate of PMOS P 23 . The drain of PMOS P 23 is the output, and is connected to ground via current source Q 22 . When voltages at the positive and negative inputs of the amplifier shown in FIG. 2 are close or equal to the supply voltage, the voltages at the drain and the source of NMOS N 21 are very close to each other, making NMOS N 21 operate in a linear region, thereby reducing the gain of the amplifier.

In order to solve the problems in the prior art, the disclosure provides a circuit and a method for overcurrent detection of a power switch.

A circuit example includes a sampling circuit and a comparing circuit. The sampling circuit is configured to perform current sampling on the power switch using a sampling Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and an amplifier, convert a sample current into a sample voltage and transmit the sample voltage to the comparing circuit, and clamp operating voltages of the comparing circuit and of an output circuit of the amplifier by a serially connected clamping MOSFET. The comparing circuit is configured to compare the sample voltage with a reference voltage and output the result of overcurrent detection.

A method example includes performing, by a sampling circuit, current sampling on the power switch using a sampling MOSFET and an amplifier, converting, by the sampling circuit, a sample current into a sample voltage and transmitting, by the sampling circuit, the sample voltage to a comparing circuit, and clamping, by a serially connected clamping MOSFET, operating voltages of the comparing circuit and of an output circuit of the amplifier; and comparing, by the comparing circuit, the sample voltage with a reference voltage and outputting, by the comparing circuit, the result of overcurrent detection.

With the circuit and method for overcurrent detection of a power switch provided by the disclosure, the sampling circuit of the overcurrent detection circuit performs current sampling on the power switch using a sampling MOSFET and an amplifier, converts a sample current into a sample voltage and transmits the sample voltage to the comparing circuit, and clamps operating voltages of the comparing circuit and of an output circuit of the amplifier by a serially connected clamping MOSFET. The comparing circuit compares the sample voltage with a reference voltage and outputs the result of overcurrent detection. Thus, overcurrent detection of a power switch can be implemented, enabling both the comparing circuit and the output circuit of the amplifier in the sampling circuit to be formed with low voltage devices.

The amplifier of the disclosure also has a structure in which the source of a PMOS of a current mirror serves as an input, and the gate voltage of an NMOS at the output is clamped by the PMOS, such that the gain of the amplifier may be increased effectively.

This section is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.

FIG. 1 is a schematic view of an overcurrent detection circuit with an NMOS as a power switch;

FIG. 2 is a schematic view of the structure of the amplifier A of FIG. 1 ;

FIG. 3 is a block diagram of an example of an overcurrent detection circuit for a power switch in accordance with some embodiments;

FIG. 4 is a schematic view of an example of an overcurrent detection circuit for a power switch in accordance with some embodiments;

FIG. 5 is a schematic view of an example of another overcurrent detection circuit for a power switch in accordance with some embodiments;

FIG. 6 is a schematic view of an example of the structure of the amplifier in an overcurrent detection circuit in accordance with some embodiments; and

FIG. 7 shows a graph of the relationship between the threshold of power switch overcurrent protection and the reference current in an example of an overcurrent detection circuit in accordance with some embodiments.

This document discloses devices and methods for overcurrent detection for a power switch. Fig. shows a block diagram of an example of an overcurrent detection circuit. As shown in FIG. 3 , the overcurrent detection circuit for a power switch includes a sampling circuit 10 and a comparing circuit 11 . The sampling circuit 10 is configured to perform current sampling on the power switch using a sampling MOSFET and an amplifier, convert a sample current into a sample voltage and transmit the sample voltage to the comparing circuit 11 , and clamp operating voltages of the comparing circuit 11 and of an output circuit of the amplifier by a serially connected clamping MOSFET. The comparing circuit 11 is configured to compare the sample voltage with a reference voltage and output the result of overcurrent detection. The power switch may be an NMOS or a PMOS. The clamping MOSFET can be an NMOS.

FIG. 4 shows a schematic diagram of an example of an overcurrent detection circuit. The circuit provides overcurrent detection for a power switch N 41 and includes a sampling circuit 10 and a comparing circuit 11 . The sampling circuit 10 includes a sampling MOSFET N 42 , an amplifier A 2 , a clamping MOSFET N 43 , a negative feedback controlling MOSFET N 44 , and a divider resistor R 41 . The sampling MOSFET N 42 and the power switch N 41 are in common-gate and common-drain connection, with both gates connected to a first bias voltage CP 1 , and both drains to an input voltage Vin. The source of sampling MOSFET N 42 is connected to a positive input of amplifier A 2 and the drain of clamping MOSFET N 43 . The source of the power switch N 41 is connected to a negative input of amplifier A 2 . The output of amplifier A 2 is connected to the gate of the negative feedback controlling MOSFET N 44 . The gate of clamping MOSFET N 43 is connected to a second bias voltage CP 2 , and the source of clamping MOSFET N 43 is connected to the divider resistor R 41 . One end of the divider resistor R 41 is connected to the source of clamping MOSFET N 43 , the power terminal of a comparator OP 2 , and a reference resistor R 42 in the comparing circuit. The other end of the divider resistor R 41 is connected to the drain of the negative feedback controlling MOSFET N 44 and the negative input of the comparator OP 2 in the comparing circuit. The source of the negative feedback controlling MOSFET N 44 is connected to ground.

The comparing circuit 11 includes reference resistor R 42 , a reference current source Q 41 , and comparator OP 2 . The common end of the reference resistor R 42 and the reference current source Q 41 is connected to the positive input of the comparator OP 2 . The power switch N 41 has a ratio of N:1 in size over the sampling MOSFET N 42 , where N is a positive integer.

During the operation of the overcurrent detection circuit shown in FIG. 4 , amplifier A 2 is connected in a negative feedback configuration. A virtual shorting effect at the input terminals of amplifier A 2 equalizes voltages at the positive and negative inputs of amplifier A 2 . The sampling MOSFET N 42 samples the current passing through the power switch N 41 , which is N times the current passing through sampling MOSFET N 42 . The current passing through the sampling MOSFET N 42 Is is the current passing through clamping MOSFET N 43 , the negative feedback controlling MOSFET N 44 , and the divider resistor R 41 . The voltage drop across the divider resistor R 41 is therefore R 41 *Is.

The voltage drop across the reference resistor R 42 is R 42 *Ir, where Ir is a reference current supplied by the reference current source Q 41 . The reference voltage Vref input at the positive input of the comparator OP 2 is the source voltage Vs of clamping MOSFET N 43 minus R 42 *Ir (or Vs−R 42 *Ir). The sample voltage Vsam input at the negative input of the comparator OP 2 is the source voltage Vs of clamping MOSFET N 43 minus R 41 *Is (or Vs−R 41 *Is).

When the current passing through power switch N 41 is small, the current passing through sampling MOSFET N 42 is also small, and R 41 *Is<R 42 *Ir. Vsam>Vref and the output signal OCP of the comparator OP 2 is low or inactive; indicating no overcurrent in the power switch N 41 . When the current passing through power switch N 41 reaches an overcurrent protection threshold then R 41 *Is>R 42 *Ir. Vsam<Vref, and the output signal OCP of the comparator OP 2 is high or active; indicating an overcurrent in the power switch N 41 .

The source voltage Vs of clamping MOSFET N 43 is the second bias voltage CP 2 minus the gate-source voltage Vgs. The second bias voltage CP 2 may be a low voltage much less than the high input voltage Vin. For example CP 2 can be 6 V. Therefore both the operating voltage of the comparing circuit and the operating voltage of the output circuit of amplifier A 2 that is formed by the negative feedback controlling MOSFET N 44 and the divider resistor R 41 are lower voltages. Therefore, all of the negative feedback controlling MOSFET N 44 , divider resistor R 41 , reference resistor R 42 , reference current source Q 41 , and comparator OP 2 may be low voltage devices. Thus, the number of high voltage devices is reduced from the circuit shown in FIG. 1 .

FIG. 5 is a schematic view of another example of an overcurrent detection circuit. The circuit provides overcurrent detection for a power switch N 51 and includes a sampling circuit 10 and a comparing circuit 11 . The sampling circuit 10 includes sampling MOSFET N 52 , amplifier A 3 , a first clamping MOSFET N 53 , a second clamping MOSFET N 55 , a negative feedback controlling MOSFET N 54 , a divider resistor R 51 , and a mirroring MOSFET N 56 . Sampling MOSFET N 52 and power switch N 51 are in common-gate and common-drain connection, with both gates connected to a first bias voltage CP 1 , and both drains to an input voltage Vin. The source of sampling MOSFET N 52 is connected to a positive input of amplifier A 3 and the drain of the first clamping MOSFET N 53 . The source of power switch N 51 is connected to a negative input of amplifier A 3 . The output of amplifier A 3 is connected to the gate of the negative feedback controlling MOSFET N 54 . The gate of the first clamping MOSFET N 53 is connected to a second bias voltage CP 2 , and the source of the first clamping MOSFET N 53 is connected to the drain of the negative feedback controlling MOSFET N 54 . The drain of the second clamping MOSFET N 55 is connected to the input voltage Vin, and the gate of the second clamping MOSFET N 55 is connected to the second bias voltage CP 2 . The source of the second clamping MOSFET N 55 is connected to the divider resistor R 51 , the power terminal of comparator OP 3 and the reference resistor R 52 of the comparing circuit. One end of the divider resistor R 51 is connected to the source of the second clamping MOSFET N 55 , the power terminal of comparator OP 3 and reference resistor R 52 of the comparing circuit. The other end of the divider resistor R 51 is connected to the drain of the mirroring MOSFET N 56 and the negative input of comparator OP 3 of the comparing circuit. The mirroring MOSFET N 56 and the negative feedback controlling MOSFET N 54 are in common-source and common-gate connection, with both sources connected to ground.

The comparing circuit 11 includes reference resistor R 52 , reference current source Q 51 , and comparator OP 3 . The common end of reference resistor R 52 and reference current source Q 51 is connected to the positive input of comparator OP 3 . The power switch N 51 has a ratio of N:1 in size over the sampling MOSFET N 52 . The power switch N 51 , sampling MOSFET N 52 , the first clamping MOSFET N 53 , the second clamping MOSFET N 55 , negative feedback controlling MOSFET N 54 , and mirroring MOSFET N 56 are all NMOSs.

During the operation of the overcurrent detection circuit shown in FIG. 5 , amplifier A 3 is connected in a negative feedback configuration, wherein a virtual shorting effect at the input terminals of amplifier A 3 equalizes voltages at the positive and negative inputs of amplifier A 3 . The sampling MOSFET N 52 samples the current passing through power switch N 51 , and the current passing through sampling MOSFET N 52 is 1/N of that through power switch N 51 . The current passing through the first clamping MOSFET N 53 and the negative feedback controlling MOSFET N 54 is the current Is passing through sampling MOSFET N 52 . The mirroring MOSFET N 56 mirrors the current Is of the negative feedback controlling MOSFET N 54 . The voltage drop across the divider resistor R 51 is R 51 *Is, where R 51 in the equation represents the resistance of R 51 in ohms. The voltage drop across reference resistor R 52 is R 52 *Ir, where R 52 in the equation represents the resistance of R 52 in ohms and Ir is the reference current supplied by reference current source Q 51 . The reference voltage Vref at the positive input of comparator OP 3 is the source voltage Vs of the second clamping MOSFET N 55 minus R 52 *Ir. The sample voltage Vsam at the negative input of comparator OP 3 is the source voltage Vs of the second clamping MOSFET N 55 minus R 51 *Is.

When the current passing through power switch N 51 is small, the current passing through sampling MOSFET N 52 is also small, and R 51 *Is<R 52 *Ir. Vsam>Vref and the output signal OCP of comparator OP 3 is low or inactive; indicating no overcurrent in power switch N 51 . When the current passing through power switch N 51 reaches an overcurrent protection threshold, R 51 *Is>R 52 *Ir and Vsam<Vref. The output signal OCP of comparator OP 3 is high or active; indicating an overcurrent in power switch N 51 .

The source voltage Vs of both the first clamping MOSFET N 53 and the second clamping MOSFET N 55 is the second bias voltage CP 2 minus the gate-source voltage Vgs. The second bias voltage CP 2 may be a low voltage much less than the input voltage Vin, such as for example 6 V. Therefore, the operating voltage of both the comparing circuit and the output circuit of amplifier A 3 that is formed by negative feedback controlling MOSFET N 54 , divider resistor R 51 , and mirroring MOSFET N 56 , are low. All of negative feedback controlling MOSFET N 54 , divider resistor R 51 , mirroring MOSFET N 56 , reference resistor R 52 , reference current source Q 51 , and comparator OP 3 may be low voltage devices.

Both the aforementioned amplifiers A 2 and A 3 may have a structure in which the source of a PMOS of a current mirror serves as an input, and the gate voltage of an NMOS at the output is clamped by the PMOS. As shown in FIG. 6 , amplifiers A 2 and A 3 may include a first PMOS P 61 , a second PMOS P 62 , a third PMOS P 63 , a fourth PMOS P 64 , a fifth PMOS P 65 , a first reference current source Q 61 , a second reference current source Q 62 , a third reference current source Q 63 , a clamping diode D 1 , a first NMOS N 61 .

The first PMOS P 61 and the second PMOS P 62 form a current mirror stage. The third PMOS P 63 and the fourth PMOS P 64 form a serial stack type stage for increasing the gain of the amplifier. The source of the first PMOS P 61 is the positive input of the amplifier, the gate of the first PMOS P 61 is connected to the drain of the first PMOS P 61 and to the gate of the second PMOS P 62 , and the drain of the first PMOS P 61 is connected to the source of the third PMOS P 63 . The source of the second PMOS P 62 is the negative input of the amplifier, the drain of the second PMOS P 62 is connected to the negative electrode of the clamping diode D 1 and the source of the fourth PMOS P 64 . The gate of the third PMOS P 63 is connected to the drain of the third PMOS P 63 and to the gate of the fourth PMOS P 64 , and the drain of the third PMOS P 63 is connected to the first reference current source Q 61 . The gate of the fourth PMOS P 64 is also connected to the positive electrode of the clamping diode D 1 . The drain of the fourth PMOS P 64 is connected to the source of the fifth PMOS P 65 , the second reference current source Q 62 , and the gate of the first NMOS N 61 . The gate of the fifth PMOS P 65 is connected to a clamping voltage Vclamp and the drain of the fifth PMOS P 65 is connected to ground. The source of the first NMOS N 61 is connected to ground and the drain of the first NMOS N 61 acts as the output of the amplifier and is connected to the third reference current source Q 63 .

The clamping diode D 1 can be configured to clamp the voltage at the node connected to the drain of the second PMOS P 62 and the source of the fourth PMOS P 64 to ensure that the voltage at that node will not be too low to exceed the allowed operating voltage ranges of the second and the fourth PMOSs P 62 and P 64 . The fifth PMOS P 65 is configured to clamp the gate voltage of the first NMOS N 61 to protect the gate of the first NMOS N 61 from overvoltage.

The aforementioned structure of the serial stack type circuit formed by the third PMOS P 63 and the fourth PMOS P 64 is illustrative only, and is optional, and does not exclude a serial stack type circuit connection formed in other structures, such as serially connected resistor R 61 at the drain of the third PMOS P 63 , connecting the gate of the first PMOS P 61 to that of the second PMOS P 62 and the common end of the drain of the third PMOS P 63 and resistor R 61 , and connecting the gate of the third PMOS P 63 to another end of resistor R 61 and the gate of the fourth PMOS P 64 .

The disclosure further provides an overcurrent detection method for a power switch. The method includes performing, by a sampling circuit, current sampling on the power switch using a sampling MOSFET and an amplifier, converting, by the sampling circuit, a sample current into a sample voltage and transmitting, by the sampling circuit, the sample voltage to a comparing circuit, and clamping, by a serially connected clamping MOSFET, operating voltages of the comparing circuit and of an output circuit of the amplifier. The method further includes comparing, by the comparing circuit, the sample voltage with a reference voltage and outputting, by the comparing circuit, the result of overcurrent detection.

The power switch may be an NMOS or a PMOS. The clamping MOSFET can be an NMOS. The sampling circuit can include the sampling MOSFET, the amplifier, the clamping MOSFET, a negative feedback controlling MOSFET, and a divider resistor. The clamping MOSFET and the divider resistor can be serially connected on a negative feedback path of the amplifier. The common end of the divider resistor and the negative feedback controlling MOSFET may output a sample voltage.

Alternatively, the sampling circuit can include the sampling MOSFET, the amplifier, a first clamping MOSFET, a second clamping MOSFET, a negative feedback controlling MOSFET, a divider resistor, and a mirroring MOSFET. The first clamping MOSFET can be serially connected on a negative feedback path of the amplifier. The second clamping MOSFET can be serially connected on the operating voltage path of a branch in which the divider resistor and the mirroring MOSFET are located. The mirroring MOSFET mirrors the current on the negative feedback controlling MOSFET, and the common end of the divider resistor and the mirroring MOSFET may output a sample voltage.

The amplifier may have a structure in which the source of a PMOS of a current mirror serves as an input, and the gate voltage of an NMOS at the output is clamped via a PMOS, as shown in FIG. 6 . The amplifier may include a first PMOS P 61 , a second PMOS P 62 , a third PMOS P 63 , a fourth PMOS P 64 , a fifth PMOS P 65 , a first reference current source Q 61 , a second reference current source Q 62 , a third reference current source Q 63 , a clamping diode D 1 , a first NMOS N 61 .

The first PMOS P 61 and the second PMOS P 62 may form a current mirror stage. The third PMOS P 63 and the fourth PMOS P 64 may form a serial stack type stage capable of increasing the gain of the amplifier. The source of the first PMOS P 61 is the positive input of the amplifier, the gate of the first PMOS P 61 is connected to the drain of the first PMOS P 61 and to the gate of the second PMOS P 62 , and the drain of the first PMOS P 61 is connected to the source of the third PMOS P 63 . The source of the second PMOS P 62 is the negative input of the amplifier, the drain of the second PMOS P 62 is connected to the negative electrode of the clamping diode D 1 and the source of the fourth PMOS P 64 . The gate of the third PMOS P 63 is connected to the drain of the third PMOS P 63 and to the gate of the fourth PMOS P 64 , and the drain of the third PMOS P 63 is connected to the first reference current source Q 61 . The gate of the fourth PMOS P 64 is also connected to the positive electrode of the clamping diode D 1 , the drain of the fourth PMOS P 64 is connected to the source of the fifth PMOS P 65 , the second reference current source Q 62 , and the gate of the first NMOS N 61 . The gate of the fifth PMOS P 65 is connected to a clamping voltage Vclamp, and the drain of the fifth PMOS P 65 is connected to ground. The source of the first NMOS N 61 is connected to ground. The drain of the first NMOS N 61 acts as the output of the amplifier and is connected to the third reference current source Q 63 .

The examples provided herein of an improved overcurrent detection circuit for a power switch can adjust the threshold for overcurrent protection of the power switch by adjusting the reference current, as shown in FIG. 7 . The x axis represents the reference current, and the y axis represents the threshold for overcurrent protection of the power switch. A linear relation is shown between the threshold for overcurrent protection of the power switch and the reference current.

To summarize, the technical solution of the disclosure can implement overcurrent detection of the power switch, and enable both the comparing circuit and the output circuit of the amplifier in the sampling circuit to be implemented as low voltage devices, and the amplifier has a structure in which the source of a PMOS of a current mirror serves as an input, and the gate voltage of an NMOS at the output is clamped by the PMOS, thereby increasing the gain of the amplifier effectively.

What are described above are merely examples and are not intended to limit the scope of the disclosure. The above description is intended to be illustrative, and not restrictive. The above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.