USPatentGranted
B2

Semiconductor device and method

Granted 2 Aug 2016 · no office action yet

Life of the patent

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Abstract

Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

Claims

20 · 3 independent · depth 5
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20 granted claims

Classifications

5 codes
IPC · International Patent Classification
Section H — Electricity
  • H01L29/78
  • H01L29/66
  • H01L27/088
  • H01L29/423
  • H01L21/20

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File wrapper

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Pendency
1.6 y
571 days filing → grant
Office actions
0
after a restriction
Examiner
Jae Lee
art unit 2899 · TC 2800
Citations: 5 back · 0 forward

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Priority chain

2 priority documents
Priority
26 Nov 2014
earliest claimed
›Priority documents — 2
TypeDocumentDate
provisionalUS 6208518226 Nov 2014
related publicationUS 20160149019 A126 May 2016

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