Semiconductor device and method
Granted 2 Aug 2016 · no office action yet
Assignee: Taiwan Semiconductor Manufacturing Company
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Attorney: Attorney · Log in to unlock
Inventors: Wai-Yi Lien, Chin-Chi Wang, Chih-Hao Wang, Shih-Cheng Chen +2 · Examiner: Jae Lee · AU 2899 · TC 2800
Life of the patent
7 dated eventsAbstract
Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.
Claims
20 · 3 independent · depth 5Classifications
5 codes- H01L29/78
- H01L29/66
- H01L27/088
- H01L29/423
- H01L21/20
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2 priority documents›Priority documents — 2
| Type | Document | Date |
|---|---|---|
| provisional | US 62085182 | 26 Nov 2014 |
| related publication | US 20160149019 A1 | 26 May 2016 |
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