Manufacturing method of semiconductor device
Granted 2 Aug 2016 · 2 office actions
Current assignee: Semiconductor Energy Laboratory Co., Ltd. · originally Semiconductor Energy Laboratory
Law firm: Law firm · Log in to unlock
Attorney: Attorney · Log in to unlock
Inventors: Hiroyuki Tomatsu, Takahiro Tsuji, Miyuki Hosoba, Masashi Tsubuku +3 · Examiner: Luan C Thai · AU 2891 · TC 2800
Life of the patent
11 dated eventsAbstract
It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
Claims
18 · 3 independent · depth 2Classifications
5 codes- H01L27/12
- H01L29/786
- H01L21/02
- H01L21/84
- H01L29/66
Claim changes
SoonSee which claims were amended, added or cancelled during examination, with every added and removed word marked.
The published claims of this patent are not paired with the granted ones in what we hold.
File wrapper
See the full prosecution history — every USPTO and applicant action on this file, in order.
Log in to unlockTerm & fees
See the term timeline — pendency span, in-force span, the maintenance fees paid and both computed expiry dates.
Log in to unlockPriority chain
1 priority documents›Priority documents — 1
| Type | Document | Date |
|---|---|---|
| related publication | US 20150044818 A1 | 12 Feb 2015 |
Validity challenges
See the validity challenges on record — reexaminations, IPRs and PGRs, with their institution decisions and outcomes.
Log in to unlockCitations
See every patent this one cites and every patent that cites it back — publication, assignee, and how each one was found.
Log in to unlock