A thin-film transistor array panel includes an insulation substrate, a gate line disposed on the insulation substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line disposed on the semiconductor layer and including a source electrode, a drain electrode disposed on the semiconductor layer and facing the source electrode, a first electrode disposed on the gate insulating layer, a first passivation layer disposed on the first electrode and including silicon nitride, a second passivation layer disposed on the first passivation and including silicon nitride, and a second electrode disposed on the passivation layer, in which a first ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the first passivation layer is different from a second ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the second passivation layer.

Claims

20 · 2 independent · depth 13

20 granted claims

›1.independentA thin-film transistor array panel, comprising:nan insulation substrate;a gate line disposed on the insulation substrate;a gate insulating layer dispo…+16

›2.↳ 1The thin-film transistor array panel of claim 1, wherein the first ratio is in a range of 22 to 24.d2+15

›3.↳ 2The thin-film transistor array panel of claim 2, wherein the first passivation layer has a thickness in a range of 200 â„« to 400 â„«.d3+14

›4.↳ 3The thin-film transistor array panel of claim 3, wherein the second ratio is in a range of 0.9 to 1.1.d4+13

›5.↳ 4The thin-film transistor array panel of claim 4, wherein the second passivation layer has a thickness in a range of 2600 â„« to 2800 â„«.d5+12

›6.↳ 5The thin-film transistor array panel of claim 5, further comprising a reference electrode line disposed on the same layer with the gate line and space…d6+11

›7.↳ 6The thin-film transistor array panel of claim 6, wherein the first electrode has a plate shape and the second electrode comprises branch electrodes.d7+10

›8.↳ 7The thin-film transistor array panel of claim 7, wherein the first electrode comprises a pixel electrode and the second electrode comprises a referenc…d8+3

›11.↳ 7The thin-film transistor array panel of claim 7, wherein the first electrode comprises a reference electrode and the second electrode comprises a pixe…d8+5

›18.independentA method of forming a thin-film transistor array panel, the method comprising:nforming a gate line on an insulation substrate;forming a gate insulatin…+2

Classifications

6 codes

IPC · International Patent Classification

Section H — Electricity

H01L29/417
H01L21/02
H01L27/14
H01L27/12
H01L29/66
H01L29/786

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1.1 y

384 days filing → grant

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Examiner

Douglas Menz

art unit 2897 · TC 2800

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