USPatentGranted
B2

Trench gate FET with self-aligned source contact

Granted 14 Jun 2016 · 2 office actions

Current assignee: NXP BV · originally NXP Semiconductors

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Inventors: Michael Petras, Pon Sung Ku, Moaniss Zitouni, Dragan Zupac +2 · Examiner: Farun Lu

Life of the patent

3 dated events
⤢ drag to zoomJul 2014Oct 2014Jan 2015Apr 2015Jul 2015Oct 2015Jan 2016Apr 2016Jul 2016Prosecution
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Abstract

A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.

Claims

16 · 2 independent · depth 3
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16 granted claims

Classifications

7 codes
IPC · International Patent Classification
Section H — Electricity
  • H01L21/265
  • H01L29/78
  • H01L21/306
  • H01L29/06
  • H01L29/40
  • H01L29/423
  • H01L29/66

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File wrapper

Pendency
1.8 y
655 days filing → grant
Office actions
1
after a restriction
Responses
1
no RCE
Examiner
Farun Lu
art unit —
Citations: 28 back · 0 forward

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Priority chain

1 priority documents
›Priority documents — 1
TypeDocumentDate
related publicationUS 20160064556 A13 Mar 2016

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Citations

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