A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.

Claims

20 · 3 independent · depth 5

20 granted claims

›1.independentA subsystem configured to perform write operations with memory cells, the subsystem comprising:na first bit line driver configured to write a data bit…+9

›2.↳ 1The subsystem of claim 1, wherein the first circuit element comprises a P-channel field effect transistor, and the second circuit element and the thir…d2

›3.↳ 1The subsystem of claim 1, further comprising:na second bit line driver configured to write the inverse of the data bit to the memory cell and includin…d2+7

›4.↳ 3The subsystem of claim 3, wherein the fourth circuit element comprises a P-channel field effect transistor, and the fifth circuit element and the sixt…d3

›5.↳ 3The subsystem of claim 3, wherein the first bit line driver further includes a seventh circuit element coupled to the third circuit element and gated …d3+2

›8.↳ 3The subsystem of claim 3, wherein the second bit line driver further includes an eighth circuit element coupled to the sixth circuit element and gated…d3+2

›11.independentA computer-implemented method for performing write operations with memory cells, the method comprising:ncausing a first write select line to activate …+3

›15.independentA computing device configured to perform write operations with memory cells, comprising:na memory cell; anda first bit line driver coupled to the memo…+5

›16.↳ 15The computing device of claim 15, further comprising:na second bit line driver coupled to the memory cell and configured to write the inverse of the d…d2+4

Classifications

1 codes

IPC · International Patent Classification

Section G — Physics

G11C11/419

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Pendency

2.0 y

735 days filing → grant

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non-final + final

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3 RCE

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Vu Le

art unit 2825 · TC 2800

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1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20150200006 A1	16 Jul 2015

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