A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

Claims

32 · 2 independent · depth 11

32 granted claims

›1.independentA monolithic three dimensional memory device, comprising:na semiconductor substrate having a major surface and a doped well region of a first conducti…+10

›2.↳ 1The monolithic three dimensional memory device of claim 1, further comprising:na plurality of electrically conductive word lines extending substantial…d2+8

›3.↳ 2The monolithic three dimensional memory device of claim 2, wherein each of the NAND memory strings comprises:na semiconductor channel, at least one en…d3+6

›4.↳ 3The monolithic three dimensional memory device of claim 3, wherein the plurality of NAND strings and at least one support member are located in an act…d4+5

›5.↳ 4The monolithic three dimensional memory device of claim 4, wherein:nthe doped well region comprises a p-well region; andeach of the source lines compr…d5+1

›7.↳ 4The monolithic three dimensional memory device of claim 4, further comprising:nat least one electrically conductive shunt line extending in a second d…d5+2

›10.↳ 2The monolithic three dimensional memory device of claim 2, wherein at least one support member is located in a word line connection region containing …d3

›11.↳ 1The monolithic three dimensional memory device of claim 1, wherein:nthe substrate comprises a silicon substrate;the plurality of NAND strings comprise…d2

›12.independentA method of making a monolithic three dimensional memory device, comprising:nforming a stack of alternating layers of a first material and a second ma…+20

›13.↳ 12The method of claim 12, wherein the doped well region comprises a p-well region.d2

›14.↳ 12The method of claim 12, wherein forming the plurality of NAND strings and forming the support pillar comprises:nforming a first insulating material la…d2+11

›15.↳ 14The method of claim 14, further comprising:nprior to forming the mask, forming a first semiconductor material layer over the tunnel dielectric layer o…d3+10

›16.↳ 15The method of claim 15, further comprising:nremoving the mask from over the top surface of the stack; andforming a second semiconductor material layer…d4+9

›17.↳ 16The method of claim 16, further comprising:nforming a core insulator layer over the second semiconductor material layer over the top surface of the st…d5+8

›18.↳ 17The method of claim 17, further comprising:netching the stack using an isotropic etching process to substantially completely remove the core insulator…d6+7

›19.↳ 18The method of claim 18, further comprising:nforming a third semiconductor material layer over the second semiconductor material layer over the top sur…d7+6

›20.↳ 19The method of claim 19, further comprising:netching the stack using an isotropic etching process to substantially completely remove the first semicond…d8+4

›21.↳ 20The method of claim 20, further comprising:netching the stack using an anisotropic etching process to remove the tunnel dielectric layer, the charge s…d9+3

›25.↳ 19The method of claim 19, wherein the third semiconductor material layer comprises an electrically conductive material that fills the support pillar ope…d8

›26.↳ 12The method of claim 12, wherein the first material in the stack comprises an insulating material and the second material in the stack comprises a sacr…d2+5

›27.↳ 26The method of claim 26, further comprising forming a blocking dielectric comprising at least one layer in the back side recesses through the at least …d3+3

›31.↳ 26The method of claim 26, wherein the support pillar is located in a word line connection region containing a plurality of word line contacts which cont…d3

›32.↳ 12The method of claim 12, further comprising forming a shunt line comprising an electrically conductive material located over the stack and extending su…d2

Classifications

9 codes

IPC · International Patent Classification

Section G — Physics

G11C16/04
G11C5/02

Section H — Electricity

H01L29/788
H01L21/768
H01L29/792
H01L29/66
H01L27/115
H01L23/528
H01L29/06

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Ly D Pham

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