A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Claims

20 · 2 independent · depth 5

20 granted claims

›1.independentA nonvolatile semiconductor memory device, comprising:na stacked structural unit including a plurality of insulating films alternately stacked with a …+15

›2.↳ 1The device according to claim 1, further comprising:na memory unit stacked film provided between the first semiconductor pillar and the electrode film…d2

›3.↳ 1The device according to claim 1, further comprising:na second semiconductor pillar adjacent to the first semiconductor pillar in a direction orthogona…d2+1

›5.↳ 1The device according to claim 1, wherein the first conducting layer includes polysilicon and an impurity added to the polysilicon.d2+4

›10.↳ 1The device according to claim 1, wherein a height of an upper end of the first semiconductor pillar substantially, equals to a height of the upper end…d2

›11.↳ 1The device according to claim 1, further comprising:na source-drain diffusion region provided in the first semiconductor pillar at a position proximal…d2

›12.↳ 1The device according to claim 1, wherein the upper end of the first core insulating unit is disposed between the upper end and a lower end of the sele…d2

›13.↳ 1The device according to claim 1, further comprising a second conducting layer,nthe first core insulating unit including a barrier insulating film,the …d2

›14.↳ 1The device according to claim 1, wherein the first semiconductor pillar includes a first portion and a second portion,na position of the first portion…d2

›15.↳ 1The device according to claim 1, whereinna first cross section of the first semiconductor pillar has an annular configuration, andthe first cross sect…d2

›16.↳ 1The device according to claim 1, whereinna width of the first semiconductor pillar in a second direction perpendicular to the first direction changes …d2

›17.independentA nonvolatile semiconductor memory device, comprising:na stacked structural unit including a plurality of insulating films alternately stacked with a …+3

Classifications

6 codes

IPC · International Patent Classification

Section H — Electricity

H01L21/223
H01L29/66
H01L21/265
H01L27/115
H01L29/792
H01L29/78

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Pendency

1.7 y

629 days filing → grant

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non-final + final

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1 RCE

Examiner

Samuel Gebremariam

art unit 2811 · TC 2800

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1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20140117434 A1	1 May 2014

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