US Patent 8,994,028 — Display device including at least six transistors

Life of the patent

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Abstract

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Claims

28 · 3 independent · depth 2

28 granted claims

›1.independentA semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a sixth t…+9

›2.↳ 1The semiconductor device according to claim 1, wherein a gate of the fourth transistor is electrically connected to the fifth wiring.d2

›3.↳ 1The semiconductor device according to claim 1, wherein a gate of the fourth transistor is electrically connected to the gate of the first transistor.d2

›4.↳ 1The semiconductor device according to claim 1, wherein a gate of the second transistor is electrically connected to a seventh wiring.d2

›5.↳ 1The semiconductor device according to claim 1, wherein a gate of the second transistor is electrically connected to the other of the source and the dr…d2

›6.↳ 1The semiconductor device according to claim 1, wherein the other of the source and the drain of the fifth transistor is electrically connected to the …d2

›7.↳ 1The semiconductor device according to claim 1, wherein the other of the source and the drain of the fifth transistor is electrically connected to an e…d2

›8.↳ 1The semiconductor device according to claim 1, wherein one of the first to sixth transistors comprises an oxide semiconductor.d2

›9.↳ 1The semiconductor device according to claim 1, wherein a clock signal is input to the fourth wiring.d2

›10.↳ 1The semiconductor device according to claim 1,nwherein the one of the source and the drain of the first transistor is directly connected to the first …d2

›11.independentA semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth trans…+9

›12.↳ 11The semiconductor device according to claim 11, wherein a gate of the fourth transistor is electrically connected to the fifth wiring.d2

›13.↳ 11The semiconductor device according to claim 11, wherein a gate of the fourth transistor is electrically connected to the gate of the first transistor.d2

›14.↳ 11The semiconductor device according to claim 11, wherein a gate of the second transistor is electrically connected to a seventh wiring.d2

›15.↳ 11The semiconductor device according to claim 11, wherein a gate of the second transistor is electrically connected to the other of the source and the d…d2

›16.↳ 11The semiconductor device according to claim 11, wherein the other of the source and the drain of the fifth transistor is electrically connected to the…d2

›17.↳ 11The semiconductor device according to claim 11, wherein the other of the source and the drain of the fifth transistor is electrically connected to an …d2

›18.↳ 11The semiconductor device according to claim 11, wherein one of the first to seventh transistors comprises an oxide semiconductor.d2

›19.↳ 11The semiconductor device according to claim 11, wherein a clock signal is input to the fourth wiring.d2

›20.↳ 11The semiconductor device according to claim 11,nwherein the one of the source and the drain of the first transistor is directly connected to the first…d2

›21.independentA semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth trans…+7

A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; and an eighth transistor,nwherein one of a source and a drain of the first transistor is electrically connected to a first wiring,wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor,wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the sixth transistor,wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor,wherein a gate of the fifth transistor is electrically connected to a fifth wiring,wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor,wherein one of a source and a drain of the seventh transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor,wherein a gate of the seventh transistor is electrically connected to a sixth wiring,wherein one of a source and a drain of the eighth transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the eighth transistor is electrically connected to the gate of the sixth transistor,wherein a gate of the eighth transistor is electrically connected to the fifth wiring, andwherein a gate of the fourth transistor is electrically connected to the gate of the first transistor.

›22.↳ 21The semiconductor device according to claim 21, wherein a gate of the second transistor is electrically connected to a seventh wiring.d2

›23.↳ 21The semiconductor device according to claim 21, wherein a gate of the second transistor is electrically connected to the other of the source and the d…d2

›24.↳ 21The semiconductor device according to claim 21, wherein the other of the source and the drain of the fifth transistor is electrically connected to the…d2

›25.↳ 21The semiconductor device according to claim 21, wherein the other of the source and the drain of the fifth transistor is electrically connected to an …d2

›26.↳ 21The semiconductor device according to claim 21, wherein one of the first to eighth transistors comprises an oxide semiconductor.d2

›27.↳ 21The semiconductor device according to claim 21, wherein a clock signal is input to the fourth wiring.d2

›28.↳ 21The semiconductor device according to claim 21,nwherein the one of the source and the drain of the first transistor is directly connected to the first…d2

The semiconductor device according to claim 21,nwherein the one of the source and the drain of the first transistor is directly connected to the first wiring,wherein the other of the source and the drain of the first transistor is directly connected to the second wiring,wherein the one of the source and the drain of the second transistor is directly connected to the third wiring,wherein the other of the source and the drain of the second transistor is directly connected to the second wiring,wherein the one of the source and the drain of the third transistor is directly connected to the fourth wiring,wherein the other of the source and the drain of the third transistor is directly connected to the gate of the sixth transistor,wherein the one of the source and the drain of the fourth transistor is directly connected to the third wiring,wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the sixth transistor,wherein the one of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor,wherein the gate of the fifth transistor is directly connected to the fifth wiring,wherein the one of the source and the drain of the sixth transistor is directly connected to the third wiring,wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the first transistor,wherein the one of the source and the drain of the seventh transistor is directly connected to the third wiring,wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the first transistor,wherein the gate of the seventh transistor is directly connected to the sixth wiring,wherein the one of the source and the drain of the eighth transistor is directly connected to the third wiring,wherein the other of the source and the drain of the eighth transistor is directly connected to the gate of the sixth transistor,wherein the gate of the eighth transistor is directly connected to the fifth wiring, andwherein the gate of the fourth transistor is directly connected to the gate of the first transistor.

Classifications

10 codes

IPC · International Patent Classification

Section G — Physics

G11C19/28
G09G3/36
G02F1/1362

Section H — Electricity

H01L27/12
H01L29/786
H01L29/423
H01L27/13
H01L27/105

USPC · US Patent Classification

257/72349/44

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Pendency

1.4 y

510 days filing → grant

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Examiner

Thomas L Dickey

art unit 2826 · TC 2800

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Priority chain

1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20140061638 A1	6 Mar 2014

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