USPatentGranted
B2

Dynamically adjusting operating frequency of a arithemetic processing device for predetermined applications based on power consumption of the memory in real time

Granted 24 Mar 2015 · 4 office actions

Assignee: Fujitsu Limited

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Inventors: Akira Naruse, Masahiro Miwa · Examiner: Thomas Lee · AU 2115 · TC 2100

Life of the patent

10 dated events
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Abstract

An information processing apparatus 1 includes a memory 13 that stores information used for arithmetic processing. The information processing apparatus 1 includes a CPU 11 that operates arithmetic processing by using the information stored in the memory 13 . The information processing apparatus 1 includes a measuring unit 15 that measures power consumption of the memory 13 . The information processing apparatus 1 includes a CPU frequency controlling unit setting unit 31 that sets an operating frequency of the CPU 11 according to the power consumption measured by the measuring unit 15.

Claims

7 · 3 independent · depth 2
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7 granted claims

Classifications

4 codes
IPC · International Patent Classification
Section G — Physics
  • G06F1/32
  • G06F1/00
USPC · US Patent Classification
713/322713/320

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File wrapper

⤢ drag to zoomJul 2012Jan 2013Jul 2013Jan 2014Jul 2014Jan 2015USPTOApplicantNon-final rejectionFinal rejectionRequest for continued examination
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Pendency
2.9 y
1,043 days filing → grant
Office actions
2
non-final + final
Responses
1
1 RCE
Interviews
1
examiner interview summaries
Examiner
Thomas Lee
art unit 2115 · TC 2100
Citations: 42 back · 0 forward

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Priority chain

1 priority documents
›Priority documents — 1
TypeDocumentDate
related publicationUS 20130024707 A124 Jan 2013

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Citations

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