Driver circuit, display device, and electronic device

A driver circuit comprising:na first transistor;a second transistor;a third transistor;a fourth transistor;a fifth transistor;a sixth transistor;a seventh transistor;an eighth transistor; anda capacitor,wherein each of the first to eighth transistors comprises a gate terminal, a source terminal, and a drain terminal,wherein one of the source terminal and the drain terminal of the first transistor is electrically connected to one of the source terminal and the drain terminal of the second transistor, one of the source terminal and the drain terminal of the third transistor, one of the source terminal and the drain terminal of the fourth transistor, and the gate terminal of the fifth transistor,wherein the gate terminal of the third transistor is electrically connected to the gate terminal of the sixth transistor,wherein one of the source terminal and the drain terminal of the fifth transistor is electrically connected to one of the source terminal and the drain terminal of the sixth transistor and is electrically connected to one of the source terminal and the drain terminal of the seventh transistor,wherein the gate terminal of the eighth transistor is electrically connected to the other one of the source terminal and the drain terminal of the first transistor and the gate terminal of the first transistor,wherein one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the gate terminal of the fourth transistor,wherein the capacitor is provided between the gate terminal of the fifth transistor and the one of the source terminal and the drain terminal of the fifth transistor, andwherein the other one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the other one of the source terminal and the drain terminal of the second transistor, the other one of the source terminal and the drain terminal of the third transistor, and the other one of the source terminal and the drain terminal of the fourth transistor.

A liquid crystal display device comprising:na pixel portion comprising:na liquid crystal element; anda transistor configured to control the liquid crystal element; anda driver circuit configured to control to the pixel portion, the driver circuit comprising:na first transistor;a second transistor;a third transistor;a fourth transistor;a fifth transistor;a sixth transistor;a seventh transistor;an eighth transistor; anda capacitor,wherein each of the first to eighth transistors comprises a gate terminal, a source terminal, and a drain terminal,wherein one of the source terminal and the drain terminal of the first transistor is electrically connected to one of the source terminal and the drain terminal of the second transistor, one of the source terminal and the drain terminal of the third transistor, one of the source terminal and the drain terminal of the fourth transistor, and the gate terminal of the fifth transistor,wherein the gate terminal of the third transistor is electrically connected to the gate terminal of the sixth transistor,wherein one of the source terminal and the drain terminal of the fifth transistor is electrically connected to one of the source terminal and the drain terminal of the sixth transistor and is electrically connected to one of the source terminal and the drain terminal of the seventh transistor,wherein the gate terminal of the eighth transistor is electrically connected to the other one of the source terminal and the drain terminal of the first transistor and the gate terminal of the first transistor,wherein one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the gate terminal of the fourth transistor,wherein the capacitor is provided between the gate terminal of the fifth transistor and the one of the source terminal and the drain terminal of the fifth transistor, andwherein the other one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the other one of the source terminal and the drain terminal of the second transistor, the other one of the source terminal and the drain terminal of the third transistor, and the other one of the source terminal and the drain terminal of the fourth transistor.

A liquid crystal display device comprising:na pixel portion comprising:na liquid crystal element; anda transistor configured to control the liquid crystal element; anda gate driver circuit configured to control to the pixel portion, the gate driver circuit comprising:na first transistor;a second transistor;a third transistor;a fourth transistor;a fifth transistor;a sixth transistor;a seventh transistor;an eighth transistor; anda capacitor,wherein each of the first to eighth transistors comprises a gate terminal, a source terminal, and a drain terminal,wherein one of the source terminal and the drain terminal of the first transistor is directly connected to one of the source terminal and the drain terminal of the second transistor, one of the source terminal and the drain terminal of the third transistor, one of the source terminal and the drain terminal of the fourth transistor, and the gate terminal of the fifth transistor,wherein the gate terminal of the third transistor is directly connected to the gate terminal of the sixth transistor,wherein one of the source terminal and the drain terminal of the fifth transistor is directly connected to one of the source terminal and the drain terminal of the sixth transistor and is directly connected to one of the source terminal and the drain terminal of the seventh transistor,wherein the gate terminal of the eighth transistor is directly connected to the other one of the source terminal and the drain terminal of the first transistor and the gate terminal of the first transistor,wherein one of the source terminal and the drain terminal of the eighth transistor is directly connected to the gate terminal of the fourth transistor,wherein the capacitor is provided between the gate terminal of the fifth transistor and the one of the source terminal and the drain terminal of the fifth transistor,wherein at least one of the first to eighth transistors comprises a channel formation region comprising an oxide semiconductor, andwherein the other one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the other one of the source terminal and the drain terminal of the second transistor, the other one of the source terminal and the drain terminal of the third transistor, and the other one of the source terminal and the drain terminal of the fourth transistor.