Methods and apparatus for Class-D amplifier circuits with D.C. offset control/correction. A Class-D amplifier is described having an output stage, such as a full H-bridge or half bridge, with a plurality of switches operable to provide a plurality of output states comprising at least a positive output state and a negative output state. Control circuitry is configured to receive a first signal based on the input signal and produce a digital control signal, which is used to determine the switch state of the output stage. A digital integrator is configured to receive a feedback signal indicative of the output state of the output stage and to sample the feedback signal at a sample rate and produce an integrated output signal (INT, IVC) indicating the difference in number of instances of the positive output state and the negative output state. Correction circuitry subtracts the integrated output signal from the input signal to produce a D.C. offset corrected signal.

Claims

43 · 5 independent · depth 6

43 granted claims

›1.independentA Class-D amplifier circuit for amplifying an input signal comprising:nan output stage comprising a plurality of switches operable to provide a plural…+38

›2.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein said feedback signal is derived from the digital control signal produced by the control circ…d2+2

›5.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein said feedback signal is derived from said control circuitry.d2

›6.↳ 1A class D-amplifier as claimed in claim 1 comprising at least one pre-driver configured to generate switch control signals for said plurality of switc…d2

›7.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein the digital integrator is operable in a first mode wherein the gain of the digital integrato…d2+6

›14.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein the amplifier is configured such that if the amplifier operation is halted then the current …d2

›15.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein the integrated output signal is digitally subtracted from a digital input signal.d2

›16.↳ 1A class-D amplifier circuit as claimed in claim 1 wherein said correction circuitry comprises a digital to analogue converter for converting the integ…d2+1

›18.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein amplifier is a pulse-density-modulated amplifier.d2+1

›20.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein the amplifier is a pulse-width-modulated amplifier.d2+11

›21.↳ 20A Class-D amplifier circuit as claimed in claim 20 wherein said control circuitry is configured so as to receive a cyclic reference signal at a first …d3+10

›22.↳ 21A Class-D amplifier circuit as claimed in claim 21 wherein said control circuitry is configured such that, within each cycle of said first clock rate,…d4

›23.↳ 21A Class-D amplifier circuit as claimed in claim 21 wherein said control circuitry is configured so as to compare said first signal to said cyclic refe…d4

›24.↳ 21A Class-D amplifier circuit as claimed in claim 21 and wherein the sample rate at which the digital integrator samples the feedback signal is greater …d4+2

›27.↳ 21A Class-D amplifier circuit as claimed in claim 21 wherein said digital integrator comprises counter circuitry for receiving said feedback signal and …d4+4

›32.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein the output stage comprises a full H-bridge stage.d2

›33.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein the output stage comprises a single-ended half bridge stage.d2

›34.↳ 1A Class-D amplifier circuit as claimed in claim 1 wherein the control circuitry comprises a quantizer.d2

›35.↳ 1An integrated circuit comprising a class-D amplifier circuit as claimed in claim 1.d2

›36.↳ 1A driver circuit comprising a class-D amplifier circuit as claimed in claim 1.d2+1

›38.↳ 1An electronic device comprising a circuit as claimed in claim 1.d2+1

›40.independentA method of correcting for D.C. offset in a Class-D amplifier having an output stage operable to provide a plurality of output states comprising at le…

›41.independentA Class-D amplifier circuit for amplifying an input signal comprising:nan output stage comprising a plurality of switches operable to provide a plural…

›42.independentA Class-D amplifier circuit for amplifying an input signal comprising:nan output stage comprising a plurality of switches operable to provide a plural…

›43.independentA Class-D amplifier circuit for amplifying an input signal comprising:nan output stage operable in at least a positive output state and a negative out…

Classifications

4 codes

IPC · International Patent Classification

Section H — Electricity

H03F3/217

USPC · US Patent Classification

330/251330/10330/207.A

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File wrapper

Pendency

2.3 y

825 days filing → grant

Office actions

after a restriction

Responses

no RCE

Examiner

Hieu Nguyen

art unit 2842 · TC 2800

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Citations: 7 back · 0 forward

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Priority chain

2 priority documents

Priority

18 Nov 2011

earliest claimed

›Priority documents — 2

Type	Document	Date
provisional	US 61561605	18 Nov 2011
related publication	US 20130127531 A1	23 May 2013

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