A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.

Claims

9 · 2 independent · depth 3

9 granted claims

›1.independentA memory device comprising:na driver circuit including a first bit line driver circuit, a second bit line driver circuit, a first word line driver cir…+4

A memory device comprising:na driver circuit including a first bit line driver circuit, a second bit line driver circuit, a first word line driver circuit, and a second word line driver circuit;a first memory cell array including a first bit line and a first word line;a second memory cell array including a second bit line and a second word line;a third memory cell array including a third bit line and the second word line; anda fourth memory cell array including a fourth bit line and the first word line with the first memory cell array,wherein:each of the first to fourth memory cell arrays overlaps with the driver circuit,the first bit line driver circuit and the second bit line driver circuit are diagonally opposite to each other in the driver circuit,the first word line driver circuit and the second word line driver circuit are diagonally opposite to each other in driver circuit,the first and second bit line driver circuits and the first and second word line driver circuits are arranged so that in data writing, a signal is transmitted across the first bit line driver circuit toward a boundary between the first word line driver circuit and the first bit line driver circuit, a signal is transmitted across the second bit line driver circuit toward a boundary between the second word line driver circuit and the second bit line driver circuit, a signal is transmitted across the first word line driver circuit toward a boundary between the first bit line driver circuit and the first word line driver circuit, and a signal is transmitted across the second word line driver circuit toward a boundary between the second bit line driver circuit and the second word line driver circuit,the first word line is electrically connected to the second word line driver circuit via a connection point provided along a boundary between the first memory cell array and the fourth memory cell array,the second word line is electrically connected to the first word line driver circuit via a connection point provided along a boundary between the second memory cell array and the third memory cell array,the first bit line and the second bit line are electrically connected to the first bit line driver circuit via connection points provided along a boundary between the first memory cell array and the second memory cell array, andthe third bit line and the fourth bit line are electrically connected to the second bit line driver circuit via connection points provided along a boundary between the third memory cell array and the fourth memory cell array.

›6.independentA memory device comprising:na driver circuit including a first bit line driver circuit, a second bit line driver circuit, a first word line driver cir…+3

A memory device comprising:na driver circuit including a first bit line driver circuit, a second bit line driver circuit, a first word line driver circuit and a second word line driver circuit;a first memory cell array including a first bit line and a first word line;a second memory cell array including a second bit line and a second word line;a third memory cell array including a third bit line and the second word line; anda fourth memory cell array including a fourth bit line and the first word line with the first memory cell array,wherein:each of the first to fourth memory cell arrays overlaps with the driver circuit,the first bit line driver circuit and the second bit line driver circuit are diagonally opposite to each other in the driver circuit,the first word line driver circuit and the second word line driver circuit are diagonally opposite to each other in driver circuit,the first bit line driver circuit comprises a first decoder, a first selector, and a first reading circuit arranged in this order, the first word line driver circuit includes a second decoder, a first level shifter, and a first buffer arranged in this order, the second bit line driver circuit includes a third decoder, a second selector, and a second reading circuit arranged in this order and the second word line driver circuit includes a fourth decoder, a second level shifter and a second buffer arranged in this order,the first word line is electrically connected to the second buffer circuit via a connection point provided along a boundary between the first memory cell array and the fourth memory cell array,the second word line is electrically connected to the first buffer via a connection point provided along a boundary between the second memory cell array and the third memory cell array,the first bit line and the second bit line are electrically connected to the first reading circuit via connection points provided along a boundary between the first memory cell array and the second memory cell array, andthe third bit line and the fourth bit line are electrically connected to the second reading circuit via connection points provided along a boundary between the third memory cell array and the fourth memory cell array.

Classifications

13 codes

IPC · International Patent Classification

Section G — Physics

G11C11/404
G11C11/4097
G11C8/08
G11C11/24

Section H — Electricity

H01L27/12
H01L27/108
H01L27/02

USPC · US Patent Classification

365/149365/191365/185.7365/185.13365/150365/230.6

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Pendency

2.1 y

783 days filing → grant

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none on record

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1 RCE

Examiner

Pho M Luu

art unit 2824 · TC 2800

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1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20130148411 A1	13 Jun 2013

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