A nitride semiconductor wafer comprising:na silicon substrate having a major surface;a lower strain relaxation layer provided on the major surface and including a nitride semiconductor, the lower strain relaxation layer having a first lattice constant;an intermediate layer provided on the lower strain relaxation layer and including a nitride semiconductor;an upper strain relaxation layer provided on the intermediate layer and including a nitride semiconductor; anda functional layer provided on the upper strain relaxation layer and including a nitride semiconductor, the intermediate layer including:a first lower layer provided on the lower strain relaxation layer and including a nitride semiconductor, the first lower layer having a second lattice constant larger than the first lattice constant;a first doped layer provided on the first lower layer and including a nitride semiconductor, the first doped layer having a third lattice constant larger than the second lattice constant and containing an impurity at a concentration of 1×1018 cm−3 or more and less than 1×1021 cm−3; anda first upper layer provided on the first doped layer and including a nitride semiconductor, the first upper layer having a fourth lattice constant larger than the third lattice constant and larger than the second lattice constant.
›2.↳ 1The wafer according to claim 1, whereinna composition ratio of the first doped layer is different from a composition ratio of the first lower layer, a…d2
The wafer according to claim 1, whereinna composition ratio of the first doped layer is different from a composition ratio of the first lower layer, and also different from a composition ratio of the first upper layer.
›3.↳ 1The wafer according to claim 1, wherein the impurity includes at least one of silicon (Si), magnesium (Mg), manganese (Mn), iron (Fe), oxygen (O), and…d2
The wafer according to claim 1, wherein the impurity includes at least one of silicon (Si), magnesium (Mg), manganese (Mn), iron (Fe), oxygen (O), and carbon (C).
›4.↳ 1The wafer according to claim 1, wherein the intermediate layer further includes:na second lower layer provided on the first upper layer and including …d2+3
The wafer according to claim 1, wherein the intermediate layer further includes:na second lower layer provided on the first upper layer and including a nitride semiconductor, the second lower layer having a fifth lattice constant smaller than the fourth lattice constant;a second doped layer provided on the second lower layer and including a nitride semiconductor, the second doped layer having a sixth lattice constant larger than or equal to the fifth lattice constant and containing an impurity at a concentration of 1×1018 cm−3 or more and less than 1×1021 cm−3; anda second upper layer provided on the second doped layer and including a nitride semiconductor, the second upper layer having a seventh lattice constant larger than or equal to the sixth lattice constant and larger than the fifth lattice constant.
›5.↳ 4The wafer according to claim 4, wherein the intermediate layer further includes a second strain relaxation layer provided between the first upper laye…d3+1
The wafer according to claim 4, wherein the intermediate layer further includes a second strain relaxation layer provided between the first upper layer and the second lower layer and including a nitride semiconductor, the second strain relaxation layer having a eighth lattice constant smaller than the fifth lattice constant.
›6.↳ 5The wafer according to claim 5, wherein the second strain relaxation layer is Alz2Ga1-z2N (0<z2≦1).d4
The wafer according to claim 5, wherein the second strain relaxation layer is Alz2Ga1-z2N (0<z2≦1).
›7.↳ 4The wafer according to claim 4, whereinnthe second lower layer includes Alxa2Inya2Ga1-xa2-ya2N (0≦xa2≦1, 0≦ya2<1, xa2+ya2≦1),the second doped …d3
The wafer according to claim 4, whereinnthe second lower layer includes Alxa2Inya2Ga1-xa2-ya2N (0≦xa2≦1, 0≦ya2<1, xa2+ya2≦1),the second doped layer includes Alxb2Inyb2Ga1-xb2-yb2N (0≦xb2<xa2, ya2≦yb2<1, xb2+yb2≦1), andthe second upper layer includes Alxc2Inyc2Ga1-xc2-yc2N (0≦xc2<xb2, yb2≦yc2<1, xc2+yc2≦1).
›8.↳ 1The wafer according to claim 1, whereinnthe first lower layer includes Alxa1Ga1-xa1N (0<xa1≦1),the first doped layer includes Alxb1Ga1-xb1N (0<xb1<x…d2
The wafer according to claim 1, whereinnthe first lower layer includes Alxa1Ga1-xa1N (0<xa1≦1),the first doped layer includes Alxb1Ga1-xb1N (0<xb1<xa1), andthe first upper layer includes Alxc1Ga1-xc1N (0≦xc1<xb1).
›9.↳ 1The wafer according to claim 1, whereinnthe lower strain relaxation layer is AlN.d2
The wafer according to claim 1, whereinnthe lower strain relaxation layer is AlN.
›10.↳ 1The wafer according to claim 1, whereinnthe upper strain relaxation layer is Alz0Ga1-z0N (0<z0≦1).d2
The wafer according to claim 1, whereinnthe upper strain relaxation layer is Alz0Ga1-z0N (0<z0≦1).
›11.↳ 1The wafer according to claim 1, whereinna thickness of the first doped layer is 20 nanometers or more and 150 nanometers or less.d2
The wafer according to claim 1, whereinna thickness of the first doped layer is 20 nanometers or more and 150 nanometers or less.
›12.↳ 1The wafer according to claim 1, whereinna thickness of the first lower layer is 100 nanometers or more and 500 nanometers or less.d2
The wafer according to claim 1, whereinna thickness of the first lower layer is 100 nanometers or more and 500 nanometers or less.
›13.↳ 1The wafer according to claim 1, whereinna thickness of the first upper layer is 100 nanometers or more and 500 nanometers or less.d2
The wafer according to claim 1, whereinna thickness of the first upper layer is 100 nanometers or more and 500 nanometers or less.
›14.↳ 1The wafer according to claim 1, whereinna first density of dislocations extending in a direction from the first lower layer toward the first upper lay…d2
The wafer according to claim 1, whereinna first density of dislocations extending in a direction from the first lower layer toward the first upper layer in the functional layer is lower than a second density of dislocations extending in the direction in the first lower layer.
›15.↳ 1The wafer according to claim 1, whereinnthe first lower layer includes Alxa1Inya1Ga1-xa1-ya1N (0≦xa1<1, 0≦ya1<1),the first doped layer includes Al…d2
The wafer according to claim 1, whereinnthe first lower layer includes Alxa1Inya1Ga1-xa1-ya1N (0≦xa1<1, 0≦ya1<1),the first doped layer includes Alxb1Inyb1Ga1-xb1-yb1N (0≦xb1<1, 0≦yb1<1),the first upper layer includes Alxc1Inyc1Ga1-xcl-yc1N (0≦xc1<1, 0≦yc1<1),the xa1 is different from the xb1 and different from the xc1 the xb1 is different from the xc1, andthe ya1 is different from the yb1 and different from the yc1, the yb1 is different from the yc1.
›16.↳ 1The wafer according to claim 1, whereinnthe first lower layer includes Alxa1Inya1Ga1-xa1-ya1N (0<xa1<1, 0≦ya1<1, xa1+ya1≦1),the first doped layer …d2
The wafer according to claim 1, whereinnthe first lower layer includes Alxa1Inya1Ga1-xa1-ya1N (0<xa1<1, 0≦ya1<1, xa1+ya1≦1),the first doped layer includes Alxb1Inyb1Ga1-xb1-yb1N (0≦xb1<1, 0≦yb1<1, xb1+yb1≦1the first upper layer includes Alxc1Inyc1Ga1-xc1-yc1N (0≦xc1<1, 0≦yc1<1, xc1+yc1≦1),the xa1 is different from the xb1 and different from the xc1, the xb1 is different from the xc1,andthe ya1 is different from the yb1 and different from the yc1 the yb1 is different from the yc1.
›17.↳ 1The wafer according to claim 1, whereinnthe first lower layer includes Alxa1Ga1-xa1N (0<xa1≦1),the first doped layer includes Alxb1Ga1-xb1N (0<xb1<x…d2
The wafer according to claim 1, whereinnthe first lower layer includes Alxa1Ga1-xa1N (0<xa1≦1),the first doped layer includes Alxb1Ga1-xb1N (0<xb1<xa1), andthe first upper layer includes Alxc1Ga1-xc1N (0≦xc1<xb1).
