A dynamically reconfigurable heterogeneous systolic array is configured to process a first image frame, and to generate image processing primatives from the image frame, and to store the primatives and the corresponding image frame in a memory store. A characteristic of the image frame is determined. Based on the characteristic, the array is reconfigured to process a following image frame.

Claims

37 · 4 independent · depth 3

37 granted claims

›1.independentAn apparatus comprising one or more hardware processors, memory, and one or more modules configured to:nprocess, in a dynamically reconfigurable heter…+11

›2.↳ 1The apparatus of claim 1, wherein an image processing primitive, of the plurality of image processing primitives, is generated by identifying a sub-re…d2

›3.↳ 1The apparatus of claim 1,nwherein the first image frame and the second image frame are video frames.d2

›4.↳ 1The apparatus of claim 1, wherein the plurality of image processing primitives comprises processed image maps or other processed hardware module data,…d2+1

›5.↳ 1The apparatus of claim 1, wherein the apparatus is also configured to provide formatted image data to a memory.d2

›7.↳ 1The apparatus of claim 1, wherein the plurality of image processing primitives comprises regional primitives or frame data primitives, or both.d2

›8.↳ 1The apparatus of claim 1, wherein the apparatus is further configured to receive formatted image data from a memory.d2

›9.↳ 1The apparatus of claim 1, wherein the apparatus further comprises a transcode module configured to receive processed image data and to provide to or r…d2+1

›11.↳ 1The apparatus of claim 1, wherein the apparatus is configured to process image data within a single clock cycle.d2

›12.↳ 1The apparatus of claim 1, wherein the apparatus is further configured to program a hardware module or an IPP module, or both.d2

›13.independentAn image acquisition and processing device comprising:na processor;a lens and image sensor for acquiring digital image frames;a dynamically reconfigur…+2

›16.independentA method, comprising:nprocessing, in a dynamically reconfigurable heterogeneous systolic array, a first image frame to generate a plurality of image p…+11

›17.↳ 16The method of claim 16, wherein an image processing primitive, of the plurality of image processing primitives, is generated by identifying a sub-regi…d2

›18.↳ 16The method of claim 16,nwherein the first image frame and the second image frame are video frames.d2

›19.↳ 16The method of claim 16, wherein the plurality of image processing primitives comprises processed image maps or other processed hardware module data, o…d2

›20.↳ 16The method of claim 16, further comprising providing formatted image data to a memory from a hardware-based image processing module.d2

›21.↳ 16The method of claim 16, further comprising processing image maps, including threshold maps or integral image maps, or both.d2

›22.↳ 16The method of claim 16, wherein the plurality of image processing primitives comprises regional primitives or frame data primitives, or both.d2

›23.↳ 16The method of claim 16, further comprising receiving formatted image data from a memory.d2

›24.↳ 16The method of claim 16, further comprising transmitting processed image data to a transcode module and communicating compressed image or video data to…d2

›25.↳ 16The method of claim 16, further comprising outputting selected subsets of image data or video data, or both, to a display.d2

›26.↳ 16The method of claim 16, further comprising processing image data within a single clock cycle with a hardware-based image processing module.d2

›27.↳ 16The method of claim 16, further comprising programming a hardware-based image processing module.d2

›28.independentA non-transitory computer-readable storage medium storing one or more instructions which, when executed by one or more processors, cause the processor…+9

›29.↳ 28The non-transitory computer-readable storage medium of claim 28, wherein the plurality of image processing primitives comprises processed image maps o…d2

›30.↳ 28The non-transitory computer-readable storage medium of claim 28 storing additional instructions which, when executed by the one or more processors, ca…d2

›31.↳ 28The non-transitory computer-readable storage medium of claim 28, storing additional instructions which, when executed by the one or more processors, c…d2

›32.↳ 28The non-transitory computer-readable storage medium of claim 28, wherein the plurality of image processing primitives comprises regional primitives or…d2

›33.↳ 28The non-transitory computer-readable storage medium of claim 28, storing additional instructions which, when executed by the one or more processors, c…d2

›34.↳ 28The non-transitory computer-readable storage medium of claim 28, storing additional instructions which, when executed by the one or more processors, c…d2

›35.↳ 28The non-transitory computer-readable storage medium of claim 28, storing additional instructions which, when executed by the one or more processors, c…d2

›36.↳ 28The non-transitory computer-readable storage medium of claim 28, storing additional instructions which, when executed by the one or more processors, c…d2+1

Classifications

8 codes

IPC · International Patent Classification

Section G — Physics

G06T1/20
G06T7/00
G06T1/00

Section H — Electricity

H04N5/335
H04N9/67
H04N5/232

USPC · US Patent Classification

382/190382/307

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3.9 y

1,426 days filing → grant

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non-final + final

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1 RCE

Examiner

Jon Chang

art unit 2665 · TC 2600

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2 priority documents

Priority

7 Jul 2010

earliest claimed

›Priority documents — 2

Type	Document	Date
provisional	US 61362247	7 Jul 2010
related publication	US 20120008002 A1	12 Jan 2012

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