A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

Claims

30 · 3 independent · depth 3

30 granted claims

›1.independentA method for forming a semiconductor structure, comprising:nforming a single masking layer on a semiconductor region;forming a trench in the semicondu…+16

›2.↳ 1The method of claim 1, wherein after the bevel etch, a width of the trench gradually decreases from a top of the trench toward a bottom of the trench.d2

›3.↳ 1The method of claim 1, wherein the trench is a first trench, the method further comprising:nforming a second trench, the mesa region being disposed be…d2

›4.↳ 1The method of claim 1, wherein the forming the trench is performed using a plasma dry etch.d2

›5.↳ 1The method of claim 1, wherein the bevel etch is performed using at least one fluorine-containing gas and at least one inert gas.d2+1

›7.↳ 1The method of claim 1, wherein the second slope is dependent on a conduction loss value L and a surface reaction loss value S.d2

›8.↳ 1The method of claim 1, wherein an angle of the second slope of the trench θ is provided by:d2+1

›10.↳ 1The method of claim 1, wherein the bevel etch does not widen a width along a bottom of the trench.d2

›11.↳ 1The method of claim 1, wherein the bevel etch does not extend a depth of the trench.d2

›12.↳ 1The method of claim 1, further comprising:nforming a gate dielectric lining the sidewall of the trench;forming a gate electrode in the trench;forming …d2

›13.↳ 1The method of claim 1, further comprising:nforming a shield dielectric lining a lower portion of the sidewall and a bottom surface of the trench;formi…d2

›14.↳ 1The method of claim 1, further comprising:ndisposing, within the trench, a silicon material having a conductivity type opposite a conductivity type of…d2

›15.↳ 1The method of claim 1, wherein the semiconductor region includes an epitaxial layer extending over a substrate, and the trench is formed in the epitax…d2

›25.↳ 1The method of claim 1, wherein the second slope is substantially constant from a top of the trench to a bottom of the trench.d2

›26.↳ 1The method of claim 1, wherein the bevel etch removes a layer of the semiconductor region in the mesa region.d2

›16.independentA method for forming a semiconductor structure, comprising:nforming a single masking layer over a semiconductor region;forming an opening in the singl…+8

›17.↳ 16The method of claim 16, wherein the trench is a first trench, the method further comprising:nforming a second trench, the mesa region being disposed b…d2

›18.↳ 16The method of claim 16, wherein forming the trench is performed using a plasma dry etch.d2

›19.↳ 16The method of claim 16, wherein the second etch is performed using at least one fluorine-containing gas and at least one inert gas.d2

›20.↳ 16The method of claim 16, wherein an angle θ of a profile of the trench is provided by:d2

›21.↳ 16The method of claim 16, further comprising:nforming a gate dielectric lining the sidewall of the trench;forming a gate electrode in the trench;forming…d2

›22.↳ 16The method of claim 16, further comprising:nforming a shield dielectric lining a lower portion of the sidewall and a bottom surface of the trench;form…d2

›23.↳ 16The method of claim 16, further comprising:ndisposing within the trench a silicon material having a conductivity type opposite a conductivity type of …d2

›24.↳ 16The method of claim 16, wherein the semiconductor region includes an epitaxial layer extending over a substrate, and the trench is formed in the epita…d2

›27.independentA method for forming a semiconductor structure, comprising:nforming a single masking layer on a semiconductor region;forming a trench in the semicondu…+3

Classifications

3 codes

IPC · International Patent Classification

Section H — Electricity

H01L21/311

USPC · US Patent Classification

438/702257/E21.628

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Calvin Choi

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Type	Document	Date
related publication	US 20090269896 A1	29 Oct 2009

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