A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

Claims

15 · 2 independent · depth 3

15 granted claims

›1.independentA power semiconductor device comprising:na semiconductor body comprising:nan active area and a peripheral area which both define a horizontal main sur…+6

›2.↳ 1The power semiconductor device of claim 1, wherein a charge carrier density per area of the fixed negative charges of the dielectric layer decreases s…d2

›3.↳ 1The power semiconductor device of claim 1, wherein the dielectric layer comprises an aluminum-doped silicon oxide and/or an aluminum-doped oxynitride.d2

›4.↳ 1The power semiconductor device of claim 1, wherein the at least one trench comprises a cavity.d2

›5.↳ 1The power semiconductor device claim 1, wherein the pn junction adjoins the dielectric layer.d2

›6.↳ 1The power semiconductor device of claim 1, wherein the dielectric layer has a negative net charge, the power semiconductor device further comprising a…d2+1

›8.independentA vertical semiconductor transistor, comprising:na semiconductor body comprising:na first n-type semiconductor region;a second semiconductor region wh…+7

›9.↳ 8The vertical semiconductor transistor of claim 8, wherein the dielectric layer extends from a main surface of the semiconductor body into the semicond…d2

›10.↳ 8The vertical semiconductor transistor of claim 8, wherein the dielectric layer comprises an aluminum-doped silicon oxide or an aluminum-doped oxynitri…d2

›11.↳ 8The vertical semiconductor transistor of claim 8, wherein the vertical semiconductor transistor is a TEDFET, and wherein the dielectric layer forms an…d2

›12.↳ 8The vertical semiconductor transistor of claim 8, wherein the dielectric layer is arranged in a vertical trench which extends from a main surface of t…d2

›13.↳ 8The vertical semiconductor transistor of claim 8, wherein a charge carrier density per area of the fixed negative charges of the dielectric layer in a…d2

›14.↳ 8The vertical semiconductor transistor of claim 8, wherein the dielectric layer has a negative net charge in the at least one portion, and wherein the …d2

›15.↳ 8The vertical semiconductor transistor of claim 8, further comprising a further dielectric layer having a positive net charge, the further dielectric l…d2

Classifications

6 codes

IPC · International Patent Classification

Section H — Electricity

H01L29/66

USPC · US Patent Classification

257/330257/E21.214257/622257/E29.262438/702

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Pendency

1.9 y

704 days filing → grant

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after a restriction

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Examiner

Elias M Ullah

art unit 2893 · TC 2800

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1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20120286355 A1	15 Nov 2012

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