Memory system including first and second caches and controlling readout of data therefrom

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the controller issues a pre-fetch request including a pre-fetch address specifying the physical address on the memory cell array to the memory interface; andthe memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories,terminates a process of the pre-fetch request without reading out data corresponding to the pre-fetch address from the memory cell array if the pre-fetch address matches the first or second address information history, andpre-fetches the data corresponding to the pre-fetch address from the memory cell array to the first or second cache region if the pre-fetch address does not match either one of the first or second address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the first cache region temporarily holds the data read out from the memory cell array, the second cache region temporarily holds the data transferred from the first cache region, the buffer memory temporarily holds the data transferred from the second cache region, andthe memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories,transfers the data held in the first cache region to the buffer memory through the second cache region, and further pre-fetches the data of the physical address succeeding the readout address from the memory cell array to the first cache region if the readout address matches the first address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the first cache region temporarily holds the data read out from the memory cell array, the second cache region temporarily holds the data transferred from the first cache region, the buffer memory temporarily holds the data transferred from the second cache region, andthe memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories,transfers the data held in the first cache region to the buffer memory through the second cache region, and further pre-fetches the data of the physical address specified by the controller from the memory cell array to the first cache region if the readout address matches the first address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the first cache region temporarily holds the data read out from the memory cell array, the second cache region temporarily holds the data transferred from the first cache region, the buffer memory temporarily holds the data transferred from the second cache region, andthe memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories,transfers the data read out from the memory cell array to the buffer memory through the first and second cache regions, and further pre-fetches the data of the physical address succeeding the readout address from the memory cell array to the first cache region if the readout address does not match either one of the first or second address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the first cache region temporarily holds the data read out from the memory cell array, the second cache region temporarily holds the data transferred from the first cache region, the buffer memory temporarily holds the data transferred from the second cache region, andthe memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories,transfers the data read out from the memory cell array to the buffer memory through the first and second cache regions, and further pre-fetches the data of the physical address specified by the controller from the memory cell array to the first cache region if the readout address does not match either one of the first or second address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories,pre-fetches the data of the physical address succeeding the readout address from the memory cell array to the first or second cache region when receiving a readout request from the controller, andhas a function of canceling the pre-fetching according to an instruction of the controller.

A memory system comprising:na memory chip including a nonvolatile memory cell array and a cache region configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage an address information history which is a physical address on the memory cell array in which the data held in the cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip; whereinthe memory interfacetransfers the data held in the cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match the address information history, andpre-fetches the data of the physical address succeeding the readout address from the memory cell array to the cache region after transferring the data read out from the memory cell array to the buffer memory through the cache region if the readout address does not match the address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and a cache region configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage an address information history which is a physical address on the memory cell array in which the data held in the cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip; whereinthe memory interfacetransfers the data held in the cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match the address information history, andpre-fetches the data of the physical address specified by the controller from the memory cell array to the cache region after transferring the data read out from the memory cell array to the buffer memory through the cache region if the readout address does not match the address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and a cache region configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage an address information history which is a physical address on the memory cell array in which the data held in the cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip; whereinthe controller issues a pre-fetch request including a pre-fetch address specifying the physical address on the memory cell array to the memory interface; andthe memory interface transfers the data held in the cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match the address information history,terminates a process of the pre-fetch request without reading out data corresponding to the pre-fetch address from the memory cell array if the pre-fetch address matches the address information history, andpre-fetches the data corresponding to the pre-fetch address from the memory cell array to the cache region if the pre-fetch address does not match the address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and a cache region configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage an address information history which is a physical address on the memory cell array in which the data held in the cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip; whereinthe memory interfacetransfers the data held in the cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match the address information history,pre-fetches the data of the physical address succeeding the readout address from the memory cell array to the cache region after transferring the data held in the cache region to the buffer memory if the readout address matches the address information history, andhas a function of canceling the pre-fetching according to an instruction of the controller.

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the controller issues a pre-fetch request including a pre-fetch address specifying the physical address on the memory cell array to the memory interface; andthe memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories, andterminates a process of the pre-fetch request without reading out data corresponding to the pre-fetch address from the memory cell array if the pre-fetch address matches the first or second address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the controller issues a pre-fetch request including a pre-fetch address specifying the physical address on the memory cell array to the memory interface; andthe memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories, andpre-fetches the data corresponding to the pre-fetch address from the memory cell array to the first or second cache region if the pre-fetch address does not match either one of the first or second address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the first cache region temporarily holds the data read out from the memory cell array, the second cache region temporarily holds the data transferred from the first cache region, the buffer memory temporarily holds the data transferred from the second cache region, andthe memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories,transfers the data held in the first cache region to the buffer memory through the second cache region, and furtherpre-fetches the data from the memory cell array to the first cache region if the readout address matches the first address information history.

A memory system comprising:na memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array;a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored;a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; anda buffer memory configured to temporarily hold the data read out from the memory chip;wherein the first cache region temporarily holds the data read out from the memory cell array, the second cache region temporarily holds the data transferred from the first cache region, the buffer memory temporarily holds the data transferred from the second cache region, andthe memory interfacetransfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history,transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history,reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories,transfers the data read out from the memory cell array to the buffer memory through the first and second cache regions, andfurther pre-fetches the data from the memory cell array to the first cache region if the readout address does not match either one of the first or second address information history.