MOS transistor, manufacturing method thereof, and semiconductor device

A method of manufacturing a MOS transistor, comprising:nforming a gate electrode over a silicon substrate in a device region defined by a device isolation region in the silicon substrate;ion-implanting first conductivity-type impurities in the silicon substrate in the device region to form a first conductivity-type source extension region and a first conductivity-type drain extension region on a first side and a second side of a channel region provided directly below the gate electrode, respectively, the first conductivity-type corresponding to n-type or p-type;forming a first offset sidewall spacer and a second offset sidewall spacer on a first sidewall and a second sidewall of the gate electrode, respectively, the first sidewall of the gate electrode being located on a first side of the channel region and the second sidewall of the gate electrode being located on a second side of the channel region;ion-implanting first conductivity-type impurities in the silicon substrate using the gate electrode and the first and second offset sidewall spacers as a mask to form a first conductivity-type source region and a first conductivity-type drain region on the first side and the second side of the channel region, respectively, such that the first conductivity-type source region is apart from the channel region and overlaps a part of the source extension region and that the first-conductivity-type drain region is apart from the channel region and overlaps a part of the drain extension region;forming a stress layer over the silicon substrate, covering the first offset sidewall spacer, the gate electrode, and the second offset sidewall spacer, the stress layer accumulating a first stress corresponding to one of a tensile stress and a compressive stress;forming a protection layer over the silicon substrate covering the stress layer;performing chemical mechanical polishing on the protection layer to expose a part of the stress layer covering the first and second offset sidewall spacers and the gate electrode;patterning by etching the exposed part of the stress layer to separate the stress layer into a first stress layer located on the first side of the channel region and extending along the first offset sidewall spacer and a second stress layer located on the second side of the channel region and extending along the second offset sidewall spacer, the first stress layer and the second stress layer accumulating the first stress, and to expose top faces of the first and second offset sidewall spacers; andremoving by etching the first and second offset sidewall spacers from the top faces thereof to produce a first gap between the first sidewall of the gate electrode and a first extending part of the first stress layer arising upward from the silicon substrate along the first sidewall of the gate electrode, and a second gap between the second sidewall of the gate electrode and a second extending part of the second stress layer arising upward from the silicon substrate along the second sidewall of the gate electrode,said first stress being the tensile stress if the first conductivity type is the n-type, and said first stress being the compressive stress if the first conductivity type is the p-type.