The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Claims

16 · 6 independent · depth 3

16 granted claims

›1.independentA manufacturing method of multi-row leadframe, comprising:nforming a plating pattern on a leadframe material (first step);forming a protective pattern…+8

›2.↳ 1The method of claim 1, wherein the first step of forming a plating pattern on the leadframe material includes: coating photosensitive material on doub…d2+1

›3.↳ 1The method of claim 1, wherein the material applied to the process of forming the plating pattern in the first step uses a single alloy from one of Ni…d2

›5.↳ 1The method of claim 1, wherein the second step includes using a photolithography method by coating the photosensitive material on double sides or a si…d2+1

›7.↳ 1The method of claim 1, wherein the protective pattern is formed in a structure encompassing an upper portion and a lateral portion of the plating patt…d2+2

›10.independentA manufacturing method of semiconductor package using multi-row leadframe, the method comprising:nforming a plating pattern on a leadframe material (f…

›11.independentA structure for multi-row leadframe in the leadframe manufacturing method, comprising:nforming at least one or more patterns on an upper surface or a …+1

›13.independentA structure for multi-row leadframe in the leadframe manufacturing method, comprising:nforming at least one or more patterns on an upper surface or a …+1

›15.independentA semiconductor package, comprising:nforming at least one or more patterns on an upper surface or a lower surface of a leadframe material; andforming …

›16.independentA semiconductor package, comprising:nforming at least one or more patterns on an upper surface or a lower surface of a leadframe material; andforming …

Classifications

10 codes

IPC · International Patent Classification

Section H — Electricity

H01L23/495
H01L21/00

USPC · US Patent Classification

438/123438/111257/666257/E23.041257/E23.005257/677257/E23.053257/E23.054

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Pendency

4.2 y

1,525 days filing → grant

Office actions

non-final + final

Responses

1 RCE

Examiner

Jasmine Clark

art unit 2815 · TC 2800

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Citations: 7 back · 0 forward

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Priority chain

1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20120038036 A1	16 Feb 2012

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