Mechanism for memory reduction in picture-in-picture video generation
Granted 4 Feb 2014 · 6 office actions
Current assignee: Wells Fargo · originally Lattice Semiconductor
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Inventors: Daekyeung Kim, Young Il Kim, Wooseung Yang, Jeoong Sung Park +1 · Examiner: Trang U Tran · AU 2422 · TC 2400
Life of the patent
3 dated eventsAbstract
A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video. The method further includes transforming the one or more other video streams into the one or more sub videos, temporarily holding the one or more sub videos in a compressed frame buffer, and merging, via pixel replacement, the main video and the one or more sub videos into a final video image capable of being displayed on a single screen utilizing a display device, wherein pixel replacement is performed such that the one or more sub videos occupy one or more sections of pixels of screen space pixels occupied by the main video.
Claims
17 · 3 independent · depth 2Classifications
3 codes- H04N5/45
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1 priority documents›Priority documents — 1
| Type | Document | Date |
|---|---|---|
| related publication | US 20110310301 A1 | 22 Dec 2011 |
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