USPatentGranted
B2

Mechanism for memory reduction in picture-in-picture video generation

Granted 4 Feb 2014 · 6 office actions

Current assignee: Wells Fargo · originally Lattice Semiconductor

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Inventors: Daekyeung Kim, Young Il Kim, Wooseung Yang, Jeoong Sung Park +1 · Examiner: Trang U Tran · AU 2422 · TC 2400

Life of the patent

3 dated events
⤢ drag to zoomJul 2010Jan 2011Jul 2011Jan 2012Jul 2012Jan 2013Jul 2013Jan 2014Prosecution
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Abstract

A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video. The method further includes transforming the one or more other video streams into the one or more sub videos, temporarily holding the one or more sub videos in a compressed frame buffer, and merging, via pixel replacement, the main video and the one or more sub videos into a final video image capable of being displayed on a single screen utilizing a display device, wherein pixel replacement is performed such that the one or more sub videos occupy one or more sections of pixels of screen space pixels occupied by the main video.

Claims

17 · 3 independent · depth 2
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17 granted claims

Classifications

3 codes
IPC · International Patent Classification
Section H — Electricity
  • H04N5/45
USPC · US Patent Classification
348/565348/567

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File wrapper

Pendency
3.6 y
1,329 days filing → grant
Office actions
3
non-final + final
Responses
3
1 RCE
Examiner
Trang U Tran
art unit 2422 · TC 2400
Citations: 10 back · 0 forward

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Priority chain

1 priority documents
›Priority documents — 1
TypeDocumentDate
related publicationUS 20110310301 A122 Dec 2011

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Citations

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